llvm/test/CodeGen/X86/atomic-or.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

29 lines
737 B
LLVM

; RUN: llc < %s -march=x86-64 -verify-machineinstrs | FileCheck %s
; rdar://9692967
define void @t1(i64* %p, i32 %b) nounwind {
entry:
%p.addr = alloca i64*, align 8
store i64* %p, i64** %p.addr, align 8
%tmp = load i64*, i64** %p.addr, align 8
; CHECK-LABEL: t1:
; CHECK: movl $2147483648, %eax
; CHECK: lock
; CHECK-NEXT: orq %r{{.*}}, (%r{{.*}})
%0 = atomicrmw or i64* %tmp, i64 2147483648 seq_cst
ret void
}
define void @t2(i64* %p, i32 %b) nounwind {
entry:
%p.addr = alloca i64*, align 8
store i64* %p, i64** %p.addr, align 8
%tmp = load i64*, i64** %p.addr, align 8
; CHECK-LABEL: t2:
; CHECK: lock
; CHECK-NEXT: orq $2147483644, (%r{{.*}})
%0 = atomicrmw or i64* %tmp, i64 2147483644 seq_cst
ret void
}