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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
132 lines
5.1 KiB
LLVM
132 lines
5.1 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=CHECK-SSE %s
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; CHECK-NOT: vunpck
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; CHECK: vinsertf128 $1
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define <8 x float> @A(<8 x float> %a) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 0, i32 1, i32 2, i32 3>
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ret <8 x float> %shuffle
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}
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; CHECK-NOT: vunpck
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; CHECK: vinsertf128 $1
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define <4 x double> @B(<4 x double> %a) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 1>
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ret <4 x double> %shuffle
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}
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declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone
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declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone
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; Just check that no crash happens
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; CHECK-SSE: _insert_crash
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define void @insert_crash() nounwind {
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allocas:
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%v1.i.i451 = shufflevector <4 x double> zeroinitializer, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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%ret_0a.i.i.i452 = shufflevector <4 x double> %v1.i.i451, <4 x double> undef, <2 x i32> <i32 0, i32 1>
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%vret_0.i.i.i454 = tail call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %ret_0a.i.i.i452, <2 x double> undef) nounwind
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%ret_val.i.i.i463 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %vret_0.i.i.i454, <2 x double> undef) nounwind
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%ret.i1.i.i464 = extractelement <2 x double> %ret_val.i.i.i463, i32 0
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%double2float = fptrunc double %ret.i1.i.i464 to float
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%smearinsert50 = insertelement <4 x float> undef, float %double2float, i32 3
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%blendAsInt.i503 = bitcast <4 x float> %smearinsert50 to <4 x i32>
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store <4 x i32> %blendAsInt.i503, <4 x i32>* undef, align 4
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ret void
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}
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;; DAG Combine must remove useless vinsertf128 instructions
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; CHECK: DAGCombineA
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; CHECK-NOT: vinsertf128 $1
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define <4 x i32> @DAGCombineA(<4 x i32> %v1) nounwind readonly {
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%1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i32> %2
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}
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; CHECK: DAGCombineB
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; CHECK: vpaddd %xmm
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; CHECK-NOT: vinsertf128 $1
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; CHECK: vpaddd %xmm
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define <8 x i32> @DAGCombineB(<8 x i32> %v1, <8 x i32> %v2) nounwind readonly {
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%1 = add <8 x i32> %v1, %v2
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%2 = add <8 x i32> %1, %v1
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ret <8 x i32> %2
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}
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; CHECK: insert_pd
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define <4 x double> @insert_pd(<4 x double> %a0, <2 x double> %a1) {
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; CHECK: vinsertf128
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%res = call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> %a0, <2 x double> %a1, i8 0)
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ret <4 x double> %res
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}
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; CHECK: insert_undef_pd
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define <4 x double> @insert_undef_pd(<4 x double> %a0, <2 x double> %a1) {
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; CHECK: vmovaps %ymm1, %ymm0
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%res = call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> undef, <2 x double> %a1, i8 0)
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ret <4 x double> %res
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}
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declare <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double>, <2 x double>, i8) nounwind readnone
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; CHECK: insert_ps
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define <8 x float> @insert_ps(<8 x float> %a0, <4 x float> %a1) {
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; CHECK: vinsertf128
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%res = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %a0, <4 x float> %a1, i8 0)
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ret <8 x float> %res
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}
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; CHECK: insert_undef_ps
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define <8 x float> @insert_undef_ps(<8 x float> %a0, <4 x float> %a1) {
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; CHECK: vmovaps %ymm1, %ymm0
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%res = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %a1, i8 0)
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ret <8 x float> %res
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}
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declare <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>, <4 x float>, i8) nounwind readnone
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; CHECK: insert_si
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define <8 x i32> @insert_si(<8 x i32> %a0, <4 x i32> %a1) {
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; CHECK: vinsertf128
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%res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> %a0, <4 x i32> %a1, i8 0)
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ret <8 x i32> %res
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}
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; CHECK: insert_undef_si
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define <8 x i32> @insert_undef_si(<8 x i32> %a0, <4 x i32> %a1) {
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; CHECK: vmovaps %ymm1, %ymm0
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%res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> undef, <4 x i32> %a1, i8 0)
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ret <8 x i32> %res
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}
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declare <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32>, <4 x i32>, i8) nounwind readnone
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; rdar://10643481
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; CHECK: vinsertf128_combine
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define <8 x float> @vinsertf128_combine(float* nocapture %f) nounwind uwtable readonly ssp {
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; CHECK-NOT: vmovaps
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; CHECK: vinsertf128
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entry:
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%add.ptr = getelementptr inbounds float, float* %f, i64 4
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%0 = bitcast float* %add.ptr to <4 x float>*
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%1 = load <4 x float>, <4 x float>* %0, align 16
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%2 = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %1, i8 1)
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ret <8 x float> %2
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}
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; rdar://11076953
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; CHECK: vinsertf128_ucombine
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define <8 x float> @vinsertf128_ucombine(float* nocapture %f) nounwind uwtable readonly ssp {
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; CHECK-NOT: vmovups
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; CHECK: vinsertf128
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entry:
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%add.ptr = getelementptr inbounds float, float* %f, i64 4
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%0 = bitcast float* %add.ptr to <4 x float>*
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%1 = load <4 x float>, <4 x float>* %0, align 8
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%2 = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %1, i8 1)
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ret <8 x float> %2
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}
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