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42317ccb5f
- Move SRA/SRL/SHL lowering support from DAG combination to DAG lowering to support extended 256-bit integer in AVX but not AVX2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177478 91177308-0d34-0410-b5e6-96231b3b80d8
47 lines
1.7 KiB
LLVM
47 lines
1.7 KiB
LLVM
; RUN: llc < %s -mtriple=i686-pc-linux -mcpu=corei7-avx | FileCheck %s
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define <8 x i32> @shiftInput___vyuunu(<8 x i32> %input, i32 %shiftval, <8 x i32> %__mask) nounwind {
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allocas:
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%smear.0 = insertelement <8 x i32> undef, i32 %shiftval, i32 0
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%smear.1 = insertelement <8 x i32> %smear.0, i32 %shiftval, i32 1
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%smear.2 = insertelement <8 x i32> %smear.1, i32 %shiftval, i32 2
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%smear.3 = insertelement <8 x i32> %smear.2, i32 %shiftval, i32 3
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%smear.4 = insertelement <8 x i32> %smear.3, i32 %shiftval, i32 4
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%smear.5 = insertelement <8 x i32> %smear.4, i32 %shiftval, i32 5
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%smear.6 = insertelement <8 x i32> %smear.5, i32 %shiftval, i32 6
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%smear.7 = insertelement <8 x i32> %smear.6, i32 %shiftval, i32 7
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%bitop = lshr <8 x i32> %input, %smear.7
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ret <8 x i32> %bitop
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}
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; CHECK: shiftInput___vyuunu
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; CHECK: psrld
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; CHECK: psrld
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; CHECK: ret
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define <8 x i32> @shiftInput___canonical(<8 x i32> %input, i32 %shiftval, <8 x i32> %__mask) nounwind {
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allocas:
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%smear.0 = insertelement <8 x i32> undef, i32 %shiftval, i32 0
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%smear.7 = shufflevector <8 x i32> %smear.0, <8 x i32> undef, <8 x i32> zeroinitializer
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%bitop = lshr <8 x i32> %input, %smear.7
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ret <8 x i32> %bitop
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}
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; CHECK: shiftInput___canonical
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; CHECK: psrld
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; CHECK: psrld
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; CHECK: ret
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define <4 x i64> @shiftInput___64in32bitmode(<4 x i64> %input, i64 %shiftval, <4 x i64> %__mask) nounwind {
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allocas:
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%smear.0 = insertelement <4 x i64> undef, i64 %shiftval, i32 0
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%smear.7 = shufflevector <4 x i64> %smear.0, <4 x i64> undef, <4 x i32> zeroinitializer
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%bitop = lshr <4 x i64> %input, %smear.7
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ret <4 x i64> %bitop
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}
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; CHECK: shiftInput___64in32bitmode
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; CHECK: psrlq
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; CHECK: psrlq
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; CHECK: ret
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