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c96096cc0f
Summary:
This required me to implement the disassembler for MIPS64r6 since the encodings
are ambiguous with other instructions. This in turn revealed a few
assembly/disassembly bugs which I have fixed.
* da[ht]i only take two operands according to the spec, not three.
* DecodeBranchTarget2[16] correctly handles wider immediates than simm16
* Also made non-functional change to DecodeBranchTarget and
DecodeBranchTargetMM to keep implementation style consistent between
them.
* Difficult encodings are handled by a custom decode method on the most
general encoding in the group. This method will convert the MCInst to a
different opcode if necessary.
DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue
so disassembling some branch instructions emit incorrect output. This seems
to affect branches with delay slots on all MIPS ISA's. I've left this bug
for now and temporarily removed the check for the immediate on
bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests.
jialc and jic crash the disassembler for some reason. I've left these
instructions commented out for the moment.
Depends on D3760
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3761
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209415 91177308-0d34-0410-b5e6-96231b3b80d8
1200 lines
43 KiB
C++
1200 lines
43 KiB
C++
//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the Mips Disassembler.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips.h"
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#include "MipsRegisterInfo.h"
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#include "MipsSubtarget.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/MemoryObject.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "mips-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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/// MipsDisassemblerBase - a disasembler class for Mips.
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class MipsDisassemblerBase : public MCDisassembler {
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public:
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/// Constructor - Initializes the disassembler.
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///
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MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
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bool bigEndian) :
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MCDisassembler(STI, Ctx),
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IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
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virtual ~MipsDisassemblerBase() {}
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bool isN64() const { return IsN64; }
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private:
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bool IsN64;
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protected:
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bool isBigEndian;
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};
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/// MipsDisassembler - a disasembler class for Mips32.
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class MipsDisassembler : public MipsDisassemblerBase {
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bool IsMicroMips;
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public:
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/// Constructor - Initializes the disassembler.
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///
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MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
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bool bigEndian) :
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MipsDisassemblerBase(STI, Ctx, bigEndian) {
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IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
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}
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bool isMips32r6() const {
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return STI.getFeatureBits() & Mips::FeatureMips32r6;
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}
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/// getInstruction - See MCDisassembler.
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DecodeStatus getInstruction(MCInst &instr,
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream,
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raw_ostream &cStream) const override;
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};
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/// Mips64Disassembler - a disasembler class for Mips64.
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class Mips64Disassembler : public MipsDisassemblerBase {
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public:
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/// Constructor - Initializes the disassembler.
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///
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Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
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bool bigEndian) :
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MipsDisassemblerBase(STI, Ctx, bigEndian) {}
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/// getInstruction - See MCDisassembler.
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DecodeStatus getInstruction(MCInst &instr,
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream,
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raw_ostream &cStream) const override;
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};
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} // end anonymous namespace
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// Forward declare these because the autogenerated code will reference them.
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// Definitions are further down.
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static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBranchTarget(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeJumpTarget(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder);
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// DecodeBranchTargetMM - Decode microMIPS branch offset, which is
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// shifted left by 1 bit.
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static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder);
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// DecodeJumpTargetMM - Decode microMIPS jump target, which is
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// shifted left by 1 bit.
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static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMem(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSimm16(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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// Decode the immediate field of an LSA instruction which
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// is off by one.
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static DecodeStatus DecodeLSAImm(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeInsSize(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeExtSize(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
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/// handle.
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template <typename InsnType>
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static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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template <typename InsnType>
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static DecodeStatus
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DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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template <typename InsnType>
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static DecodeStatus
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DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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template <typename InsnType>
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static DecodeStatus
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DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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template <typename InsnType>
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static DecodeStatus
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DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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template <typename InsnType>
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static DecodeStatus
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DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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namespace llvm {
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extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
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TheMips64elTarget;
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}
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static MCDisassembler *createMipsDisassembler(
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const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new MipsDisassembler(STI, Ctx, true);
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}
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static MCDisassembler *createMipselDisassembler(
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const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new MipsDisassembler(STI, Ctx, false);
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}
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static MCDisassembler *createMips64Disassembler(
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const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new Mips64Disassembler(STI, Ctx, true);
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}
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static MCDisassembler *createMips64elDisassembler(
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const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new Mips64Disassembler(STI, Ctx, false);
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}
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extern "C" void LLVMInitializeMipsDisassembler() {
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// Register the disassembler.
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TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
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createMipsDisassembler);
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TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
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createMipselDisassembler);
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TargetRegistry::RegisterMCDisassembler(TheMips64Target,
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createMips64Disassembler);
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TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
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createMips64elDisassembler);
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}
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#include "MipsGenDisassemblerTables.inc"
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static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
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const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
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const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
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return *(RegInfo->getRegClass(RC).begin() + RegNo);
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}
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template <typename InsnType>
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static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder) {
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typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
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// The size of the n field depends on the element size
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// The register class also depends on this.
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InsnType tmp = fieldFromInstruction(insn, 17, 5);
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unsigned NSize = 0;
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DecodeFN RegDecoder = nullptr;
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if ((tmp & 0x18) == 0x00) { // INSVE_B
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NSize = 4;
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RegDecoder = DecodeMSA128BRegisterClass;
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} else if ((tmp & 0x1c) == 0x10) { // INSVE_H
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NSize = 3;
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RegDecoder = DecodeMSA128HRegisterClass;
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} else if ((tmp & 0x1e) == 0x18) { // INSVE_W
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NSize = 2;
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RegDecoder = DecodeMSA128WRegisterClass;
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} else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
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NSize = 1;
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RegDecoder = DecodeMSA128DRegisterClass;
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} else
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llvm_unreachable("Invalid encoding");
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assert(NSize != 0 && RegDecoder != nullptr);
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// $wd
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tmp = fieldFromInstruction(insn, 6, 5);
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if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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// $wd_in
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if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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// $n
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tmp = fieldFromInstruction(insn, 16, NSize);
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MI.addOperand(MCOperand::CreateImm(tmp));
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// $ws
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tmp = fieldFromInstruction(insn, 11, 5);
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if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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// $n2
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MI.addOperand(MCOperand::CreateImm(0));
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return MCDisassembler::Success;
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}
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template <typename InsnType>
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static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
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uint64_t Address,
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const void *Decoder) {
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// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
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// (otherwise we would have matched the ADDI instruction from the earlier
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// ISA's instead).
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//
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// We have:
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// 0b001000 sssss ttttt iiiiiiiiiiiiiiii
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// BOVC if rs >= rt
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// BEQZALC if rs == 0 && rt != 0
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// BEQC if rs < rt && rs != 0
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InsnType Rs = fieldFromInstruction(insn, 21, 5);
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InsnType Rt = fieldFromInstruction(insn, 16, 5);
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InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
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bool HasRs = false;
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if (Rs >= Rt) {
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MI.setOpcode(Mips::BOVC);
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HasRs = true;
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} else if (Rs != 0 && Rs < Rt) {
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MI.setOpcode(Mips::BEQC);
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HasRs = true;
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} else
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MI.setOpcode(Mips::BEQZALC);
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if (HasRs)
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MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
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Rs)));
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MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
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Rt)));
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MI.addOperand(MCOperand::CreateImm(Imm));
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return MCDisassembler::Success;
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}
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template <typename InsnType>
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static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
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uint64_t Address,
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const void *Decoder) {
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// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
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// (otherwise we would have matched the ADDI instruction from the earlier
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// ISA's instead).
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//
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// We have:
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// 0b011000 sssss ttttt iiiiiiiiiiiiiiii
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// BNVC if rs >= rt
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// BNEZALC if rs == 0 && rt != 0
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// BNEC if rs < rt && rs != 0
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InsnType Rs = fieldFromInstruction(insn, 21, 5);
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InsnType Rt = fieldFromInstruction(insn, 16, 5);
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InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
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bool HasRs = false;
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if (Rs >= Rt) {
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MI.setOpcode(Mips::BNVC);
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HasRs = true;
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} else if (Rs != 0 && Rs < Rt) {
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MI.setOpcode(Mips::BNEC);
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HasRs = true;
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} else
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MI.setOpcode(Mips::BNEZALC);
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if (HasRs)
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MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
|
|
Rs)));
|
|
|
|
MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
|
|
Rt)));
|
|
MI.addOperand(MCOperand::CreateImm(Imm));
|
|
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
template <typename InsnType>
|
|
static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
|
|
// (otherwise we would have matched the BLEZL instruction from the earlier
|
|
// ISA's instead).
|
|
//
|
|
// We have:
|
|
// 0b010110 sssss ttttt iiiiiiiiiiiiiiii
|
|
// Invalid if rs == 0
|
|
// BLEZC if rs == 0 && rt != 0
|
|
// BGEZC if rs == rt && rt != 0
|
|
// BGEC if rs != rt && rs != 0 && rt != 0
|
|
|
|
InsnType Rs = fieldFromInstruction(insn, 21, 5);
|
|
InsnType Rt = fieldFromInstruction(insn, 16, 5);
|
|
InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
|
|
|
|
if (Rt == 0)
|
|
return MCDisassembler::Fail;
|
|
else if (Rs == 0)
|
|
MI.setOpcode(Mips::BLEZC);
|
|
else if (Rs == Rt)
|
|
MI.setOpcode(Mips::BGEZC);
|
|
else
|
|
return MCDisassembler::Fail; // FIXME: BGEC is not implemented yet.
|
|
|
|
MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
|
|
Rt)));
|
|
|
|
MI.addOperand(MCOperand::CreateImm(Imm));
|
|
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
template <typename InsnType>
|
|
static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
|
|
// (otherwise we would have matched the BGTZL instruction from the earlier
|
|
// ISA's instead).
|
|
//
|
|
// We have:
|
|
// 0b010111 sssss ttttt iiiiiiiiiiiiiiii
|
|
// Invalid if rs == 0
|
|
// BGTZC if rs == 0 && rt != 0
|
|
// BLTZC if rs == rt && rt != 0
|
|
// BLTC if rs != rt && rs != 0 && rt != 0
|
|
|
|
InsnType Rs = fieldFromInstruction(insn, 21, 5);
|
|
InsnType Rt = fieldFromInstruction(insn, 16, 5);
|
|
InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
|
|
|
|
if (Rt == 0)
|
|
return MCDisassembler::Fail;
|
|
else if (Rs == 0)
|
|
MI.setOpcode(Mips::BGTZC);
|
|
else if (Rs == Rt)
|
|
MI.setOpcode(Mips::BLTZC);
|
|
else
|
|
return MCDisassembler::Fail; // FIXME: BLTC is not implemented yet.
|
|
|
|
MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
|
|
Rt)));
|
|
|
|
MI.addOperand(MCOperand::CreateImm(Imm));
|
|
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
template <typename InsnType>
|
|
static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
|
|
// (otherwise we would have matched the BGTZ instruction from the earlier
|
|
// ISA's instead).
|
|
//
|
|
// We have:
|
|
// 0b000111 sssss ttttt iiiiiiiiiiiiiiii
|
|
// BGTZ if rt == 0
|
|
// BGTZALC if rs == 0 && rt != 0
|
|
// BLTZALC if rs != 0 && rs == rt
|
|
// BLTUC if rs != 0 && rs != rt
|
|
|
|
InsnType Rs = fieldFromInstruction(insn, 21, 5);
|
|
InsnType Rt = fieldFromInstruction(insn, 16, 5);
|
|
InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
|
|
bool HasRs = false;
|
|
bool HasRt = false;
|
|
|
|
if (Rt == 0) {
|
|
MI.setOpcode(Mips::BGTZ);
|
|
HasRs = true;
|
|
} else if (Rs == 0) {
|
|
MI.setOpcode(Mips::BGTZALC);
|
|
HasRt = true;
|
|
} else if (Rs == Rt) {
|
|
MI.setOpcode(Mips::BLTZALC);
|
|
HasRs = true;
|
|
} else
|
|
return MCDisassembler::Fail; // BLTUC not implemented yet
|
|
|
|
if (HasRs)
|
|
MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
|
|
Rs)));
|
|
|
|
if (HasRt)
|
|
MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
|
|
Rt)));
|
|
|
|
MI.addOperand(MCOperand::CreateImm(Imm));
|
|
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
/// readInstruction - read four bytes from the MemoryObject
|
|
/// and return 32 bit word sorted according to the given endianess
|
|
static DecodeStatus readInstruction32(const MemoryObject ®ion,
|
|
uint64_t address,
|
|
uint64_t &size,
|
|
uint32_t &insn,
|
|
bool isBigEndian,
|
|
bool IsMicroMips) {
|
|
uint8_t Bytes[4];
|
|
|
|
// We want to read exactly 4 Bytes of data.
|
|
if (region.readBytes(address, 4, Bytes) == -1) {
|
|
size = 0;
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
if (isBigEndian) {
|
|
// Encoded as a big-endian 32-bit word in the stream.
|
|
insn = (Bytes[3] << 0) |
|
|
(Bytes[2] << 8) |
|
|
(Bytes[1] << 16) |
|
|
(Bytes[0] << 24);
|
|
}
|
|
else {
|
|
// Encoded as a small-endian 32-bit word in the stream.
|
|
// Little-endian byte ordering:
|
|
// mips32r2: 4 | 3 | 2 | 1
|
|
// microMIPS: 2 | 1 | 4 | 3
|
|
if (IsMicroMips) {
|
|
insn = (Bytes[2] << 0) |
|
|
(Bytes[3] << 8) |
|
|
(Bytes[0] << 16) |
|
|
(Bytes[1] << 24);
|
|
} else {
|
|
insn = (Bytes[0] << 0) |
|
|
(Bytes[1] << 8) |
|
|
(Bytes[2] << 16) |
|
|
(Bytes[3] << 24);
|
|
}
|
|
}
|
|
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
DecodeStatus
|
|
MipsDisassembler::getInstruction(MCInst &instr,
|
|
uint64_t &Size,
|
|
const MemoryObject &Region,
|
|
uint64_t Address,
|
|
raw_ostream &vStream,
|
|
raw_ostream &cStream) const {
|
|
uint32_t Insn;
|
|
|
|
DecodeStatus Result = readInstruction32(Region, Address, Size,
|
|
Insn, isBigEndian, IsMicroMips);
|
|
if (Result == MCDisassembler::Fail)
|
|
return MCDisassembler::Fail;
|
|
|
|
if (IsMicroMips) {
|
|
// Calling the auto-generated decoder function.
|
|
Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
|
|
this, STI);
|
|
if (Result != MCDisassembler::Fail) {
|
|
Size = 4;
|
|
return Result;
|
|
}
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
if (isMips32r6()) {
|
|
Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
|
|
Address, this, STI);
|
|
if (Result != MCDisassembler::Fail) {
|
|
Size = 4;
|
|
return Result;
|
|
}
|
|
}
|
|
|
|
// Calling the auto-generated decoder function.
|
|
Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
|
|
this, STI);
|
|
if (Result != MCDisassembler::Fail) {
|
|
Size = 4;
|
|
return Result;
|
|
}
|
|
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
DecodeStatus
|
|
Mips64Disassembler::getInstruction(MCInst &instr,
|
|
uint64_t &Size,
|
|
const MemoryObject &Region,
|
|
uint64_t Address,
|
|
raw_ostream &vStream,
|
|
raw_ostream &cStream) const {
|
|
uint32_t Insn;
|
|
|
|
DecodeStatus Result = readInstruction32(Region, Address, Size,
|
|
Insn, isBigEndian, false);
|
|
if (Result == MCDisassembler::Fail)
|
|
return MCDisassembler::Fail;
|
|
|
|
// Calling the auto-generated decoder function.
|
|
Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
|
|
this, STI);
|
|
if (Result != MCDisassembler::Fail) {
|
|
Size = 4;
|
|
return Result;
|
|
}
|
|
// If we fail to decode in Mips64 decoder space we can try in Mips32
|
|
Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
|
|
this, STI);
|
|
if (Result != MCDisassembler::Fail) {
|
|
Size = 4;
|
|
return Result;
|
|
}
|
|
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
|
|
return MCDisassembler::Fail;
|
|
|
|
}
|
|
|
|
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
|
|
if (RegNo > 31)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
if (RegNo > 31)
|
|
return MCDisassembler::Fail;
|
|
unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
|
|
return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
|
|
|
|
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
|
|
}
|
|
|
|
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
|
|
}
|
|
|
|
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
if (RegNo > 31)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
if (RegNo > 31)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
if (RegNo > 31)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
if (RegNo > 31)
|
|
return MCDisassembler::Fail;
|
|
unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
if (RegNo > 7)
|
|
return MCDisassembler::Fail;
|
|
unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeMem(MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
int Offset = SignExtend32<16>(Insn & 0xffff);
|
|
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
|
|
unsigned Base = fieldFromInstruction(Insn, 21, 5);
|
|
|
|
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
|
|
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
|
|
|
|
if(Inst.getOpcode() == Mips::SC){
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
}
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
Inst.addOperand(MCOperand::CreateReg(Base));
|
|
Inst.addOperand(MCOperand::CreateImm(Offset));
|
|
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder) {
|
|
int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
|
|
unsigned Reg = fieldFromInstruction(Insn, 6, 5);
|
|
unsigned Base = fieldFromInstruction(Insn, 11, 5);
|
|
|
|
Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
|
|
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
Inst.addOperand(MCOperand::CreateReg(Base));
|
|
|
|
// The immediate field of an LD/ST instruction is scaled which means it must
|
|
// be multiplied (when decoding) by the size (in bytes) of the instructions'
|
|
// data format.
|
|
// .b - 1 byte
|
|
// .h - 2 bytes
|
|
// .w - 4 bytes
|
|
// .d - 8 bytes
|
|
switch(Inst.getOpcode())
|
|
{
|
|
default:
|
|
assert (0 && "Unexpected instruction");
|
|
return MCDisassembler::Fail;
|
|
break;
|
|
case Mips::LD_B:
|
|
case Mips::ST_B:
|
|
Inst.addOperand(MCOperand::CreateImm(Offset));
|
|
break;
|
|
case Mips::LD_H:
|
|
case Mips::ST_H:
|
|
Inst.addOperand(MCOperand::CreateImm(Offset << 1));
|
|
break;
|
|
case Mips::LD_W:
|
|
case Mips::ST_W:
|
|
Inst.addOperand(MCOperand::CreateImm(Offset << 2));
|
|
break;
|
|
case Mips::LD_D:
|
|
case Mips::ST_D:
|
|
Inst.addOperand(MCOperand::CreateImm(Offset << 3));
|
|
break;
|
|
}
|
|
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
int Offset = SignExtend32<12>(Insn & 0x0fff);
|
|
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
|
|
unsigned Base = fieldFromInstruction(Insn, 16, 5);
|
|
|
|
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
|
|
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
|
|
|
|
if (Inst.getOpcode() == Mips::SC_MM)
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
Inst.addOperand(MCOperand::CreateReg(Base));
|
|
Inst.addOperand(MCOperand::CreateImm(Offset));
|
|
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
int Offset = SignExtend32<16>(Insn & 0xffff);
|
|
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
|
|
unsigned Base = fieldFromInstruction(Insn, 16, 5);
|
|
|
|
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
|
|
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
Inst.addOperand(MCOperand::CreateReg(Base));
|
|
Inst.addOperand(MCOperand::CreateImm(Offset));
|
|
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeFMem(MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
int Offset = SignExtend32<16>(Insn & 0xffff);
|
|
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
|
|
unsigned Base = fieldFromInstruction(Insn, 21, 5);
|
|
|
|
Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
|
|
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
|
|
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
Inst.addOperand(MCOperand::CreateReg(Base));
|
|
Inst.addOperand(MCOperand::CreateImm(Offset));
|
|
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
|
|
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
// Currently only hardware register 29 is supported.
|
|
if (RegNo != 29)
|
|
return MCDisassembler::Fail;
|
|
Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
if (RegNo > 30 || RegNo %2)
|
|
return MCDisassembler::Fail;
|
|
|
|
;
|
|
unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
if (RegNo >= 4)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
if (RegNo >= 4)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
if (RegNo >= 4)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
if (RegNo > 31)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
if (RegNo > 31)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
if (RegNo > 31)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
if (RegNo > 31)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
if (RegNo > 7)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
|
|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
if (RegNo > 31)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
|
|
Inst.addOperand(MCOperand::CreateReg(Reg));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeBranchTarget(MCInst &Inst,
|
|
unsigned Offset,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
int32_t BranchOffset = (SignExtend32<16>(Offset) << 2) + 4;
|
|
Inst.addOperand(MCOperand::CreateImm(BranchOffset));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeJumpTarget(MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
|
|
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
|
|
Inst.addOperand(MCOperand::CreateImm(JumpOffset));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
|
|
unsigned Offset,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
int32_t BranchOffset = SignExtend32<21>(Offset) << 2;
|
|
|
|
Inst.addOperand(MCOperand::CreateImm(BranchOffset));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
|
|
unsigned Offset,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
int32_t BranchOffset = SignExtend32<26>(Offset) << 2;
|
|
|
|
Inst.addOperand(MCOperand::CreateImm(BranchOffset));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
|
|
unsigned Offset,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
int32_t BranchOffset = SignExtend32<16>(Offset) << 1;
|
|
Inst.addOperand(MCOperand::CreateImm(BranchOffset));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
|
|
Inst.addOperand(MCOperand::CreateImm(JumpOffset));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeSimm16(MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeLSAImm(MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
// We add one to the immediate field as it was encoded as 'imm - 1'.
|
|
Inst.addOperand(MCOperand::CreateImm(Insn + 1));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeInsSize(MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
// First we need to grab the pos(lsb) from MCInst.
|
|
int Pos = Inst.getOperand(2).getImm();
|
|
int Size = (int) Insn - Pos + 1;
|
|
Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeExtSize(MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
int Size = (int) Insn + 1;
|
|
Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder) {
|
|
Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2));
|
|
return MCDisassembler::Success;
|
|
}
|