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c9672cb8be
registers for a given virtual register. Reserved registers are filtered from the allocation order, and any valid hint is returned as the first suggestion. For target dependent hints, a number of arcane target hooks are invoked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121497 91177308-0d34-0410-b5e6-96231b3b80d8
507 lines
19 KiB
C++
507 lines
19 KiB
C++
//===-- llvm/CodeGen/VirtRegMap.h - Virtual Register Map -*- C++ -*--------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a virtual register map. This maps virtual registers to
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// physical registers and virtual registers to stack slots. It is created and
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// updated by a register allocator and then used by a machine code rewriter that
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// adds spill code and rewrites virtual into physical register references.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_VIRTREGMAP_H
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#define LLVM_CODEGEN_VIRTREGMAP_H
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include <map>
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namespace llvm {
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class LiveIntervals;
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class MachineInstr;
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class MachineFunction;
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class MachineRegisterInfo;
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class TargetInstrInfo;
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class TargetRegisterInfo;
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class raw_ostream;
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class VirtRegMap : public MachineFunctionPass {
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public:
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enum {
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NO_PHYS_REG = 0,
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NO_STACK_SLOT = (1L << 30)-1,
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MAX_STACK_SLOT = (1L << 18)-1
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};
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enum ModRef { isRef = 1, isMod = 2, isModRef = 3 };
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typedef std::multimap<MachineInstr*,
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std::pair<unsigned, ModRef> > MI2VirtMapTy;
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private:
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MachineRegisterInfo *MRI;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineFunction *MF;
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DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs;
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/// Virt2PhysMap - This is a virtual to physical register
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/// mapping. Each virtual register is required to have an entry in
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/// it; even spilled virtual registers (the register mapped to a
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/// spilled register is the temporary used to load it from the
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/// stack).
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IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysMap;
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/// Virt2StackSlotMap - This is virtual register to stack slot
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/// mapping. Each spilled virtual register has an entry in it
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/// which corresponds to the stack slot this register is spilled
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/// at.
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IndexedMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap;
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/// Virt2ReMatIdMap - This is virtual register to rematerialization id
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/// mapping. Each spilled virtual register that should be remat'd has an
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/// entry in it which corresponds to the remat id.
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IndexedMap<int, VirtReg2IndexFunctor> Virt2ReMatIdMap;
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/// Virt2SplitMap - This is virtual register to splitted virtual register
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/// mapping.
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IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2SplitMap;
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/// Virt2SplitKillMap - This is splitted virtual register to its last use
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/// (kill) index mapping.
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IndexedMap<SlotIndex> Virt2SplitKillMap;
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/// ReMatMap - This is virtual register to re-materialized instruction
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/// mapping. Each virtual register whose definition is going to be
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/// re-materialized has an entry in it.
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IndexedMap<MachineInstr*, VirtReg2IndexFunctor> ReMatMap;
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/// MI2VirtMap - This is MachineInstr to virtual register
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/// mapping. In the case of memory spill code being folded into
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/// instructions, we need to know which virtual register was
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/// read/written by this instruction.
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MI2VirtMapTy MI2VirtMap;
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/// SpillPt2VirtMap - This records the virtual registers which should
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/// be spilled right after the MachineInstr due to live interval
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/// splitting.
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std::map<MachineInstr*, std::vector<std::pair<unsigned,bool> > >
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SpillPt2VirtMap;
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/// RestorePt2VirtMap - This records the virtual registers which should
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/// be restored right before the MachineInstr due to live interval
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/// splitting.
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std::map<MachineInstr*, std::vector<unsigned> > RestorePt2VirtMap;
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/// EmergencySpillMap - This records the physical registers that should
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/// be spilled / restored around the MachineInstr since the register
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/// allocator has run out of registers.
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std::map<MachineInstr*, std::vector<unsigned> > EmergencySpillMap;
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/// EmergencySpillSlots - This records emergency spill slots used to
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/// spill physical registers when the register allocator runs out of
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/// registers. Ideally only one stack slot is used per function per
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/// register class.
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std::map<const TargetRegisterClass*, int> EmergencySpillSlots;
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/// ReMatId - Instead of assigning a stack slot to a to be rematerialized
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/// virtual register, an unique id is being assigned. This keeps track of
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/// the highest id used so far. Note, this starts at (1<<18) to avoid
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/// conflicts with stack slot numbers.
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int ReMatId;
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/// LowSpillSlot, HighSpillSlot - Lowest and highest spill slot indexes.
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int LowSpillSlot, HighSpillSlot;
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/// SpillSlotToUsesMap - Records uses for each register spill slot.
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SmallVector<SmallPtrSet<MachineInstr*, 4>, 8> SpillSlotToUsesMap;
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/// ImplicitDefed - One bit for each virtual register. If set it indicates
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/// the register is implicitly defined.
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BitVector ImplicitDefed;
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/// UnusedRegs - A list of physical registers that have not been used.
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BitVector UnusedRegs;
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/// createSpillSlot - Allocate a spill slot for RC from MFI.
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unsigned createSpillSlot(const TargetRegisterClass *RC);
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VirtRegMap(const VirtRegMap&); // DO NOT IMPLEMENT
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void operator=(const VirtRegMap&); // DO NOT IMPLEMENT
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public:
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static char ID;
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VirtRegMap() : MachineFunctionPass(ID), Virt2PhysMap(NO_PHYS_REG),
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Virt2StackSlotMap(NO_STACK_SLOT),
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Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0),
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Virt2SplitKillMap(SlotIndex()), ReMatMap(NULL),
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ReMatId(MAX_STACK_SLOT+1),
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LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) { }
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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MachineFunction &getMachineFunction() const {
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assert(MF && "getMachineFunction called before runOnMachineFunction");
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return *MF;
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}
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MachineRegisterInfo &getRegInfo() const { return *MRI; }
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const TargetRegisterInfo &getTargetRegInfo() const { return *TRI; }
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void grow();
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/// @brief returns true if the specified virtual register is
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/// mapped to a physical register
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bool hasPhys(unsigned virtReg) const {
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return getPhys(virtReg) != NO_PHYS_REG;
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}
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/// @brief returns the physical register mapped to the specified
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/// virtual register
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unsigned getPhys(unsigned virtReg) const {
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assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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return Virt2PhysMap[virtReg];
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}
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/// @brief creates a mapping for the specified virtual register to
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/// the specified physical register
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void assignVirt2Phys(unsigned virtReg, unsigned physReg) {
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assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
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TargetRegisterInfo::isPhysicalRegister(physReg));
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assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
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"attempt to assign physical register to already mapped "
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"virtual register");
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Virt2PhysMap[virtReg] = physReg;
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}
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/// @brief clears the specified virtual register's, physical
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/// register mapping
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void clearVirt(unsigned virtReg) {
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assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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assert(Virt2PhysMap[virtReg] != NO_PHYS_REG &&
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"attempt to clear a not assigned virtual register");
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Virt2PhysMap[virtReg] = NO_PHYS_REG;
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}
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/// @brief clears all virtual to physical register mappings
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void clearAllVirt() {
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Virt2PhysMap.clear();
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grow();
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}
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/// @brief returns the register allocation preference.
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unsigned getRegAllocPref(unsigned virtReg);
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/// @brief records virtReg is a split live interval from SReg.
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void setIsSplitFromReg(unsigned virtReg, unsigned SReg) {
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Virt2SplitMap[virtReg] = SReg;
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}
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/// @brief returns the live interval virtReg is split from.
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unsigned getPreSplitReg(unsigned virtReg) {
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return Virt2SplitMap[virtReg];
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}
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/// @brief returns true if the specified virtual register is not
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/// mapped to a stack slot or rematerialized.
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bool isAssignedReg(unsigned virtReg) const {
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if (getStackSlot(virtReg) == NO_STACK_SLOT &&
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getReMatId(virtReg) == NO_STACK_SLOT)
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return true;
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// Split register can be assigned a physical register as well as a
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// stack slot or remat id.
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return (Virt2SplitMap[virtReg] && Virt2PhysMap[virtReg] != NO_PHYS_REG);
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}
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/// @brief returns the stack slot mapped to the specified virtual
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/// register
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int getStackSlot(unsigned virtReg) const {
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assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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return Virt2StackSlotMap[virtReg];
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}
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/// @brief returns the rematerialization id mapped to the specified virtual
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/// register
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int getReMatId(unsigned virtReg) const {
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assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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return Virt2ReMatIdMap[virtReg];
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}
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/// @brief create a mapping for the specifed virtual register to
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/// the next available stack slot
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int assignVirt2StackSlot(unsigned virtReg);
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/// @brief create a mapping for the specified virtual register to
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/// the specified stack slot
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void assignVirt2StackSlot(unsigned virtReg, int frameIndex);
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/// @brief assign an unique re-materialization id to the specified
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/// virtual register.
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int assignVirtReMatId(unsigned virtReg);
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/// @brief assign an unique re-materialization id to the specified
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/// virtual register.
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void assignVirtReMatId(unsigned virtReg, int id);
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/// @brief returns true if the specified virtual register is being
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/// re-materialized.
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bool isReMaterialized(unsigned virtReg) const {
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return ReMatMap[virtReg] != NULL;
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}
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/// @brief returns the original machine instruction being re-issued
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/// to re-materialize the specified virtual register.
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MachineInstr *getReMaterializedMI(unsigned virtReg) const {
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return ReMatMap[virtReg];
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}
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/// @brief records the specified virtual register will be
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/// re-materialized and the original instruction which will be re-issed
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/// for this purpose. If parameter all is true, then all uses of the
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/// registers are rematerialized and it's safe to delete the definition.
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void setVirtIsReMaterialized(unsigned virtReg, MachineInstr *def) {
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ReMatMap[virtReg] = def;
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}
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/// @brief record the last use (kill) of a split virtual register.
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void addKillPoint(unsigned virtReg, SlotIndex index) {
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Virt2SplitKillMap[virtReg] = index;
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}
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SlotIndex getKillPoint(unsigned virtReg) const {
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return Virt2SplitKillMap[virtReg];
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}
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/// @brief remove the last use (kill) of a split virtual register.
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void removeKillPoint(unsigned virtReg) {
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Virt2SplitKillMap[virtReg] = SlotIndex();
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}
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/// @brief returns true if the specified MachineInstr is a spill point.
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bool isSpillPt(MachineInstr *Pt) const {
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return SpillPt2VirtMap.find(Pt) != SpillPt2VirtMap.end();
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}
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/// @brief returns the virtual registers that should be spilled due to
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/// splitting right after the specified MachineInstr.
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std::vector<std::pair<unsigned,bool> > &getSpillPtSpills(MachineInstr *Pt) {
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return SpillPt2VirtMap[Pt];
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}
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/// @brief records the specified MachineInstr as a spill point for virtReg.
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void addSpillPoint(unsigned virtReg, bool isKill, MachineInstr *Pt) {
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std::map<MachineInstr*, std::vector<std::pair<unsigned,bool> > >::iterator
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I = SpillPt2VirtMap.find(Pt);
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if (I != SpillPt2VirtMap.end())
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I->second.push_back(std::make_pair(virtReg, isKill));
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else {
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std::vector<std::pair<unsigned,bool> > Virts;
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Virts.push_back(std::make_pair(virtReg, isKill));
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SpillPt2VirtMap.insert(std::make_pair(Pt, Virts));
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}
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}
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/// @brief - transfer spill point information from one instruction to
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/// another.
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void transferSpillPts(MachineInstr *Old, MachineInstr *New) {
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std::map<MachineInstr*, std::vector<std::pair<unsigned,bool> > >::iterator
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I = SpillPt2VirtMap.find(Old);
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if (I == SpillPt2VirtMap.end())
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return;
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while (!I->second.empty()) {
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unsigned virtReg = I->second.back().first;
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bool isKill = I->second.back().second;
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I->second.pop_back();
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addSpillPoint(virtReg, isKill, New);
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}
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SpillPt2VirtMap.erase(I);
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}
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/// @brief returns true if the specified MachineInstr is a restore point.
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bool isRestorePt(MachineInstr *Pt) const {
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return RestorePt2VirtMap.find(Pt) != RestorePt2VirtMap.end();
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}
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/// @brief returns the virtual registers that should be restoreed due to
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/// splitting right after the specified MachineInstr.
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std::vector<unsigned> &getRestorePtRestores(MachineInstr *Pt) {
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return RestorePt2VirtMap[Pt];
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}
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/// @brief records the specified MachineInstr as a restore point for virtReg.
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void addRestorePoint(unsigned virtReg, MachineInstr *Pt) {
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std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
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RestorePt2VirtMap.find(Pt);
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if (I != RestorePt2VirtMap.end())
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I->second.push_back(virtReg);
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else {
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std::vector<unsigned> Virts;
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Virts.push_back(virtReg);
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RestorePt2VirtMap.insert(std::make_pair(Pt, Virts));
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}
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}
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/// @brief - transfer restore point information from one instruction to
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/// another.
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void transferRestorePts(MachineInstr *Old, MachineInstr *New) {
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std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
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RestorePt2VirtMap.find(Old);
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if (I == RestorePt2VirtMap.end())
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return;
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while (!I->second.empty()) {
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unsigned virtReg = I->second.back();
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I->second.pop_back();
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addRestorePoint(virtReg, New);
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}
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RestorePt2VirtMap.erase(I);
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}
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/// @brief records that the specified physical register must be spilled
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/// around the specified machine instr.
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void addEmergencySpill(unsigned PhysReg, MachineInstr *MI) {
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if (EmergencySpillMap.find(MI) != EmergencySpillMap.end())
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EmergencySpillMap[MI].push_back(PhysReg);
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else {
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std::vector<unsigned> PhysRegs;
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PhysRegs.push_back(PhysReg);
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EmergencySpillMap.insert(std::make_pair(MI, PhysRegs));
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}
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}
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/// @brief returns true if one or more physical registers must be spilled
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/// around the specified instruction.
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bool hasEmergencySpills(MachineInstr *MI) const {
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return EmergencySpillMap.find(MI) != EmergencySpillMap.end();
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}
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/// @brief returns the physical registers to be spilled and restored around
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/// the instruction.
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std::vector<unsigned> &getEmergencySpills(MachineInstr *MI) {
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return EmergencySpillMap[MI];
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}
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/// @brief - transfer emergency spill information from one instruction to
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/// another.
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void transferEmergencySpills(MachineInstr *Old, MachineInstr *New) {
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std::map<MachineInstr*,std::vector<unsigned> >::iterator I =
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EmergencySpillMap.find(Old);
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if (I == EmergencySpillMap.end())
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return;
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while (!I->second.empty()) {
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unsigned virtReg = I->second.back();
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I->second.pop_back();
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addEmergencySpill(virtReg, New);
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}
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EmergencySpillMap.erase(I);
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}
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/// @brief return or get a emergency spill slot for the register class.
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int getEmergencySpillSlot(const TargetRegisterClass *RC);
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/// @brief Return lowest spill slot index.
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int getLowSpillSlot() const {
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return LowSpillSlot;
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}
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/// @brief Return highest spill slot index.
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int getHighSpillSlot() const {
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return HighSpillSlot;
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}
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/// @brief Records a spill slot use.
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void addSpillSlotUse(int FrameIndex, MachineInstr *MI);
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/// @brief Returns true if spill slot has been used.
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bool isSpillSlotUsed(int FrameIndex) const {
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assert(FrameIndex >= 0 && "Spill slot index should not be negative!");
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return !SpillSlotToUsesMap[FrameIndex-LowSpillSlot].empty();
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}
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/// @brief Mark the specified register as being implicitly defined.
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void setIsImplicitlyDefined(unsigned VirtReg) {
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ImplicitDefed.set(VirtReg-TargetRegisterInfo::FirstVirtualRegister);
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}
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/// @brief Returns true if the virtual register is implicitly defined.
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bool isImplicitlyDefined(unsigned VirtReg) const {
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return ImplicitDefed[VirtReg-TargetRegisterInfo::FirstVirtualRegister];
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}
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/// @brief Updates information about the specified virtual register's value
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/// folded into newMI machine instruction.
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void virtFolded(unsigned VirtReg, MachineInstr *OldMI, MachineInstr *NewMI,
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ModRef MRInfo);
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/// @brief Updates information about the specified virtual register's value
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/// folded into the specified machine instruction.
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void virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo);
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/// @brief returns the virtual registers' values folded in memory
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/// operands of this instruction
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std::pair<MI2VirtMapTy::const_iterator, MI2VirtMapTy::const_iterator>
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getFoldedVirts(MachineInstr* MI) const {
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return MI2VirtMap.equal_range(MI);
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}
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/// RemoveMachineInstrFromMaps - MI is being erased, remove it from the
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/// the folded instruction map and spill point map.
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void RemoveMachineInstrFromMaps(MachineInstr *MI);
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/// FindUnusedRegisters - Gather a list of allocatable registers that
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/// have not been allocated to any virtual register.
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bool FindUnusedRegisters(LiveIntervals* LIs);
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/// HasUnusedRegisters - Return true if there are any allocatable registers
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/// that have not been allocated to any virtual register.
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bool HasUnusedRegisters() const {
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return !UnusedRegs.none();
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}
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/// setRegisterUsed - Remember the physical register is now used.
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void setRegisterUsed(unsigned Reg) {
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UnusedRegs.reset(Reg);
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}
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/// isRegisterUnused - Return true if the physical register has not been
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/// used.
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bool isRegisterUnused(unsigned Reg) const {
|
|
return UnusedRegs[Reg];
|
|
}
|
|
|
|
/// getFirstUnusedRegister - Return the first physical register that has not
|
|
/// been used.
|
|
unsigned getFirstUnusedRegister(const TargetRegisterClass *RC) {
|
|
int Reg = UnusedRegs.find_first();
|
|
while (Reg != -1) {
|
|
if (allocatableRCRegs[RC][Reg])
|
|
return (unsigned)Reg;
|
|
Reg = UnusedRegs.find_next(Reg);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void print(raw_ostream &OS, const Module* M = 0) const;
|
|
void dump() const;
|
|
};
|
|
|
|
inline raw_ostream &operator<<(raw_ostream &OS, const VirtRegMap &VRM) {
|
|
VRM.print(OS);
|
|
return OS;
|
|
}
|
|
} // End llvm namespace
|
|
|
|
#endif
|