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The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8
84 lines
3.3 KiB
C++
84 lines
3.3 KiB
C++
//===- NVPTXInstrInfo.h - NVPTX Instruction Information----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the niversity of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the NVPTX implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef NVPTXINSTRUCTIONINFO_H
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#define NVPTXINSTRUCTIONINFO_H
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#include "NVPTX.h"
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#include "NVPTXRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "NVPTXGenInstrInfo.inc"
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namespace llvm {
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class NVPTXInstrInfo : public NVPTXGenInstrInfo
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{
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NVPTXTargetMachine &TM;
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const NVPTXRegisterInfo RegInfo;
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public:
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explicit NVPTXInstrInfo(NVPTXTargetMachine &TM);
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virtual const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
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/* The following virtual functions are used in register allocation.
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* They are not implemented because the existing interface and the logic
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* at the caller side do not work for the elementized vector load and store.
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*
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* virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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* int &FrameIndex) const;
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* virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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* int &FrameIndex) const;
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* virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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* MachineBasicBlock::iterator MBBI,
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* unsigned SrcReg, bool isKill, int FrameIndex,
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* const TargetRegisterClass *RC) const;
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* virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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* MachineBasicBlock::iterator MBBI,
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* unsigned DestReg, int FrameIndex,
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* const TargetRegisterClass *RC) const;
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*/
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const ;
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virtual bool isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg,
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unsigned &DestReg) const;
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bool isLoadInstr(const MachineInstr &MI, unsigned &AddrSpace) const;
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bool isStoreInstr(const MachineInstr &MI, unsigned &AddrSpace) const;
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bool isReadSpecialReg(MachineInstr &MI) const;
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virtual bool CanTailMerge(const MachineInstr *MI) const ;
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// Branch analysis.
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const {
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return MI.getOperand(2).getImm();
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}
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};
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} // namespace llvm
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#endif
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