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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
192 lines
4.1 KiB
LLVM
192 lines
4.1 KiB
LLVM
; RUN: llc -march=sparc <%s | FileCheck %s -check-prefix=V8
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; RUN: llc -march=sparc -mattr=v9 <%s | FileCheck %s -check-prefix=V9
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; RUN: llc -mtriple=sparc64-unknown-linux <%s | FileCheck %s -check-prefix=SPARC64
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define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind readnone noinline {
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entry:
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; V8: addcc
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; V8-NOT: subcc
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; V8: addx
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; V9: addcc
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; V9-NOT: subcc
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; V9: addx
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; V9: mov{{e|ne}} %icc
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%0 = add i64 %a, %b
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%1 = icmp ugt i64 %0, %c
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind readnone noinline {
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entry:
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; V8: test_select_int_icc
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; V8: cmp
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; V8: {{be|bne}}
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; V9: test_select_int_icc
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; V9: cmp
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; V9-NOT: {{be|bne}}
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; V9: mov{{e|ne}} %icc
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%0 = icmp eq i32 %a, 0
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%1 = select i1 %0, i32 %b, i32 %c
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ret i32 %1
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}
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define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind readnone noinline {
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entry:
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; V8: test_select_fp_icc
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; V8: cmp
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; V8: {{be|bne}}
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; V9: test_select_fp_icc
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; V9: cmp
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; V9-NOT: {{be|bne}}
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; V9: fmovs{{e|ne}} %icc
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%0 = icmp eq i32 %a, 0
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%1 = select i1 %0, float %f1, float %f2
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ret float %1
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}
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define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind readnone noinline {
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entry:
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; V8: test_select_dfp_icc
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; V8: cmp
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; V8: {{be|bne}}
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; V9: test_select_dfp_icc
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; V9: cmp
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; V9-NOT: {{be|bne}}
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; V9: fmovd{{e|ne}} %icc
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%0 = icmp eq i32 %a, 0
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%1 = select i1 %0, double %f1, double %f2
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ret double %1
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}
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define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind readnone noinline {
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entry:
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;V8-LABEL: test_select_int_fcc:
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;V8: fcmps
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;V8-NEXT: nop
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;V8: {{fbe|fbne}}
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;V9-LABEL: test_select_int_fcc:
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;V9: fcmps
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;V9-NEXT-NOT: nop
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;V9-NOT: {{fbe|fbne}}
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;V9: mov{{e|ne}} %fcc0
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%0 = fcmp une float %f, 0.000000e+00
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%a.b = select i1 %0, i32 %a, i32 %b
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ret i32 %a.b
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}
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define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind readnone noinline {
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entry:
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;V8-LABEL: test_select_fp_fcc:
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;V8: fcmps
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;V8: {{fbe|fbne}}
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;V9-LABEL: test_select_fp_fcc:
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;V9: fcmps
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;V9-NOT: {{fbe|fbne}}
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;V9: fmovs{{e|ne}} %fcc0
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%0 = fcmp une float %f, 0.000000e+00
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%1 = select i1 %0, float %f1, float %f2
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ret float %1
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}
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define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind readnone noinline {
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entry:
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;V8-LABEL: test_select_dfp_fcc:
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;V8: fcmpd
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;V8-NEXT: nop
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;V8: {{fbne|fbe}}
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;V9-LABEL: test_select_dfp_fcc:
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;V9: fcmpd
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;V9-NEXT-NOT: nop
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;V9-NOT: {{fbne|fbe}}
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;V9: fmovd{{e|ne}} %fcc0
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%0 = fcmp une double %f, 0.000000e+00
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%1 = select i1 %0, double %f1, double %f2
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ret double %1
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}
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define i32 @test_float_cc(double %a, double %b, i32 %c, i32 %d) {
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entry:
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; V8-LABEL: test_float_cc
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; V8: fcmpd
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; V8: {{fbl|fbuge}} .LBB
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; V8: fcmpd
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; V8: {{fbule|fbg}} .LBB
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; V9-LABEL: test_float_cc
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; V9: fcmpd
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; V9: {{fbl|fbuge}} .LBB
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; V9: fcmpd
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; V9: {{fbule|fbg}} .LBB
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%0 = fcmp uge double %a, 0.000000e+00
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br i1 %0, label %loop, label %loop.2
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loop:
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%1 = icmp eq i32 %c, 10
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br i1 %1, label %loop, label %exit.0
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loop.2:
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%2 = fcmp ogt double %b, 0.000000e+00
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br i1 %2, label %exit.1, label %loop
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exit.0:
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ret i32 0
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exit.1:
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ret i32 1
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}
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; V8-LABEL: test_adde_sube
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; V8: addcc
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; V8: addxcc
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; V8: addxcc
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; V8: addxcc
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; V8: subcc
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; V8: subxcc
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; V8: subxcc
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; V8: subxcc
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; V9-LABEL: test_adde_sube
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; V9: addcc
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; V9: addxcc
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; V9: addxcc
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; V9: addxcc
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; V9: subcc
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; V9: subxcc
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; V9: subxcc
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; V9: subxcc
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; SPARC64-LABEL: test_adde_sube
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; SPARC64: addcc
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; SPARC64: addxcc
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; SPARC64: addxcc
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; SPARC64: addxcc
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; SPARC64: subcc
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; SPARC64: subxcc
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; SPARC64: subxcc
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; SPARC64: subxcc
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define void @test_adde_sube(i8* %a, i8* %b, i8* %sum, i8* %diff) {
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entry:
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%0 = bitcast i8* %a to i128*
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%1 = bitcast i8* %b to i128*
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%2 = load i128, i128* %0
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%3 = load i128, i128* %1
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%4 = add i128 %2, %3
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%5 = bitcast i8* %sum to i128*
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store i128 %4, i128* %5
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tail call void asm sideeffect "", "=*m,*m"(i128 *%0, i128* %5) nounwind
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%6 = load i128, i128* %0
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%7 = sub i128 %2, %6
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%8 = bitcast i8* %diff to i128*
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store i128 %7, i128* %8
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ret void
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}
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