Tim Northover dca70119b4 ARM: disallow pc as a base register in Thumb2 memory ops. ... These should all be deferring to the "OP (literal)" variant according to the ARM ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261895 91177308-0d34-0410-b5e6-96231b3b80d8		2016-02-25 16:54:52 +00:00
..
AArch64	AArch64: remove CRC feature from Cyclone.	2016-02-24 18:10:17 +00:00
AMDGPU	[AMDGPU] Fix operands of S_BFE_U64 and S_BFM_B64	2016-02-23 09:19:14 +00:00
ARM	ARM: disallow pc as a base register in Thumb2 memory ops.	2016-02-25 16:54:52 +00:00
AsmParser	[MC] Fixed parsing of macro arguments where expressions with spaces are present.	2016-02-11 13:48:49 +00:00
COFF	[codeview] Dump def range lengths in hex	2016-02-11 23:40:14 +00:00
Disassembler	[AMDGPU] Disassembler: Support for all VOP1 instructions.	2016-02-25 16:09:14 +00:00
ELF	Accept subtractions involving a weak symbol.	2016-01-20 18:57:48 +00:00
Hexagon	[Hexagon] Adding relocation for code size, cold path optimization allowing a 23-bit 4-byte aligned relocation to be a valid instruction encoding.	2016-02-16 20:38:17 +00:00
MachO
Markup
Mips	[mips][microMIPS] Implement DINSU, DINSM, DINS instructions	2016-02-25 12:53:29 +00:00
PowerPC	[MC] Merge VK_PPC_TPREL in to generic VK_TPREL.	2016-02-10 18:32:01 +00:00
Sparc	[SPARC] Repair floating-point condition encodings in assembly parser.	2016-02-10 17:47:20 +00:00
SystemZ
X86	AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx . Change memory operand parser handling.	2016-02-25 13:30:17 +00:00