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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17238 91177308-0d34-0410-b5e6-96231b3b80d8
700 lines
26 KiB
C++
700 lines
26 KiB
C++
//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveInterval analysis pass which is used
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// by the Linear Scan Register allocator. This pass linearizes the
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// basic blocks of the function in DFS order and uses the
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// LiveVariables pass to conservatively compute live intervals for
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// each virtual and physical register.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "liveintervals"
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#include "LiveIntervalAnalysis.h"
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#include "VirtRegMap.h"
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#include "llvm/Value.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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#include <algorithm>
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#include <cmath>
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using namespace llvm;
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namespace {
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RegisterAnalysis<LiveIntervals> X("liveintervals", "Live Interval Analysis");
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Statistic<> numIntervals
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("liveintervals", "Number of original intervals");
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Statistic<> numIntervalsAfter
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("liveintervals", "Number of intervals after coalescing");
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Statistic<> numJoins
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("liveintervals", "Number of interval joins performed");
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Statistic<> numPeep
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("liveintervals", "Number of identity moves eliminated after coalescing");
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Statistic<> numFolded
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("liveintervals", "Number of loads/stores folded into instructions");
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cl::opt<bool>
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EnableJoining("join-liveintervals",
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cl::desc("Join compatible live intervals"),
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cl::init(true));
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};
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void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
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{
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AU.addPreserved<LiveVariables>();
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AU.addRequired<LiveVariables>();
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AU.addPreservedID(PHIEliminationID);
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AU.addRequiredID(PHIEliminationID);
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AU.addRequiredID(TwoAddressInstructionPassID);
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AU.addRequired<LoopInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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void LiveIntervals::releaseMemory()
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{
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mi2iMap_.clear();
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i2miMap_.clear();
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r2iMap_.clear();
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r2rMap_.clear();
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}
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/// runOnMachineFunction - Register allocate the whole function
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///
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bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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mf_ = &fn;
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tm_ = &fn.getTarget();
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mri_ = tm_->getRegisterInfo();
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lv_ = &getAnalysis<LiveVariables>();
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allocatableRegs_ = mri_->getAllocatableSet(fn);
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r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
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// number MachineInstrs
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unsigned miIndex = 0;
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for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end();
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mbb != mbbEnd; ++mbb)
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for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
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mi != miEnd; ++mi) {
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bool inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second;
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assert(inserted && "multiple MachineInstr -> index mappings");
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i2miMap_.push_back(mi);
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miIndex += InstrSlots::NUM;
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}
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computeIntervals();
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numIntervals += getNumIntervals();
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#if 1
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DEBUG(std::cerr << "********** INTERVALS **********\n");
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DEBUG(for (iterator I = begin(), E = end(); I != E; ++I)
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std::cerr << I->second << "\n");
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#endif
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// join intervals if requested
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if (EnableJoining) joinIntervals();
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numIntervalsAfter += getNumIntervals();
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// perform a final pass over the instructions and compute spill
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// weights, coalesce virtual registers and remove identity moves
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const LoopInfo& loopInfo = getAnalysis<LoopInfo>();
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const TargetInstrInfo& tii = *tm_->getInstrInfo();
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for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
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mbbi != mbbe; ++mbbi) {
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MachineBasicBlock* mbb = mbbi;
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unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
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for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
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mii != mie; ) {
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// if the move will be an identity move delete it
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unsigned srcReg, dstReg, RegRep;
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if (tii.isMoveInstr(*mii, srcReg, dstReg) &&
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(RegRep = rep(srcReg)) == rep(dstReg)) {
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// remove from def list
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LiveInterval &interval = getOrCreateInterval(RegRep);
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// remove index -> MachineInstr and
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// MachineInstr -> index mappings
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Mi2IndexMap::iterator mi2i = mi2iMap_.find(mii);
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if (mi2i != mi2iMap_.end()) {
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i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
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mi2iMap_.erase(mi2i);
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}
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mii = mbbi->erase(mii);
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++numPeep;
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}
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else {
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for (unsigned i = 0; i < mii->getNumOperands(); ++i) {
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const MachineOperand& mop = mii->getOperand(i);
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if (mop.isRegister() && mop.getReg() &&
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MRegisterInfo::isVirtualRegister(mop.getReg())) {
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// replace register with representative register
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unsigned reg = rep(mop.getReg());
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mii->SetMachineOperandReg(i, reg);
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LiveInterval &RegInt = getInterval(reg);
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RegInt.weight +=
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(mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth);
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}
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}
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++mii;
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}
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}
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}
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DEBUG(dump());
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return true;
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}
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/// print - Implement the dump method.
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void LiveIntervals::print(std::ostream &O) const {
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O << "********** INTERVALS **********\n";
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for (const_iterator I = begin(), E = end(); I != E; ++I)
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O << " " << I->second << "\n";
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O << "********** MACHINEINSTRS **********\n";
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for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
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mbbi != mbbe; ++mbbi) {
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O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
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for (MachineBasicBlock::iterator mii = mbbi->begin(),
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mie = mbbi->end(); mii != mie; ++mii) {
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O << getInstructionIndex(mii) << '\t' << *mii;
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}
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}
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}
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std::vector<LiveInterval*> LiveIntervals::
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addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
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// since this is called after the analysis is done we don't know if
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// LiveVariables is available
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lv_ = getAnalysisToUpdate<LiveVariables>();
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std::vector<LiveInterval*> added;
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assert(li.weight != HUGE_VAL &&
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"attempt to spill already spilled interval!");
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DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: "
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<< li << '\n');
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const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
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for (LiveInterval::Ranges::const_iterator
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i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
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unsigned index = getBaseIndex(i->start);
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unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM;
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for (; index != end; index += InstrSlots::NUM) {
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// skip deleted instructions
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while (index != end && !getInstructionFromIndex(index))
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index += InstrSlots::NUM;
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if (index == end) break;
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MachineBasicBlock::iterator mi = getInstructionFromIndex(index);
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for_operand:
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for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
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MachineOperand& mop = mi->getOperand(i);
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if (mop.isRegister() && mop.getReg() == li.reg) {
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// First thing, attempt to fold the memory reference into the
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// instruction. If we can do this, we don't need to insert spill
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// code.
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if (MachineInstr* fmi = mri_->foldMemoryOperand(mi, i, slot)) {
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if (lv_)
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lv_->instructionChanged(mi, fmi);
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vrm.virtFolded(li.reg, mi, i, fmi);
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mi2iMap_.erase(mi);
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i2miMap_[index/InstrSlots::NUM] = fmi;
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mi2iMap_[fmi] = index;
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MachineBasicBlock &MBB = *mi->getParent();
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mi = MBB.insert(MBB.erase(mi), fmi);
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++numFolded;
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// Folding the load/store can completely change the instruction in
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// unpredictable ways, rescan it from the beginning.
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goto for_operand;
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} else {
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// This is tricky. We need to add information in the interval about
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// the spill code so we have to use our extra load/store slots.
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//
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// If we have a use we are going to have a load so we start the
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// interval from the load slot onwards. Otherwise we start from the
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// def slot.
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unsigned start = (mop.isUse() ?
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getLoadIndex(index) :
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getDefIndex(index));
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// If we have a def we are going to have a store right after it so
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// we end the interval after the use of the next
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// instruction. Otherwise we end after the use of this instruction.
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unsigned end = 1 + (mop.isDef() ?
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getStoreIndex(index) :
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getUseIndex(index));
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// create a new register for this spill
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unsigned nReg = mf_->getSSARegMap()->createVirtualRegister(rc);
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mi->SetMachineOperandReg(i, nReg);
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vrm.grow();
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vrm.assignVirt2StackSlot(nReg, slot);
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LiveInterval& nI = getOrCreateInterval(nReg);
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assert(nI.empty());
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// the spill weight is now infinity as it
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// cannot be spilled again
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nI.weight = HUGE_VAL;
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LiveRange LR(start, end, nI.getNextValue());
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DEBUG(std::cerr << " +" << LR);
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nI.addRange(LR);
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added.push_back(&nI);
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// update live variables if it is available
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if (lv_)
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lv_->addVirtualRegisterKilled(nReg, mi);
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DEBUG(std::cerr << "\t\t\t\tadded new interval: " << nI << '\n');
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}
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}
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}
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}
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}
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return added;
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}
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void LiveIntervals::printRegName(unsigned reg) const
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{
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if (MRegisterInfo::isPhysicalRegister(reg))
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std::cerr << mri_->getName(reg);
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else
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std::cerr << "%reg" << reg;
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}
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void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock* mbb,
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MachineBasicBlock::iterator mi,
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LiveInterval& interval)
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{
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DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
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LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
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// Virtual registers may be defined multiple times (due to phi
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// elimination and 2-addr elimination). Much of what we do only has to be
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// done once for the vreg. We use an empty interval to detect the first
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// time we see a vreg.
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if (interval.empty()) {
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// Get the Idx of the defining instructions.
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unsigned defIndex = getDefIndex(getInstructionIndex(mi));
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unsigned ValNum = interval.getNextValue();
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assert(ValNum == 0 && "First value in interval is not 0?");
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ValNum = 0; // Clue in the optimizer.
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// Loop over all of the blocks that the vreg is defined in. There are
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// two cases we have to handle here. The most common case is a vreg
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// whose lifetime is contained within a basic block. In this case there
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// will be a single kill, in MBB, which comes after the definition.
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if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
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// FIXME: what about dead vars?
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unsigned killIdx;
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if (vi.Kills[0] != mi)
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killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
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else
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killIdx = defIndex+1;
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// If the kill happens after the definition, we have an intra-block
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// live range.
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if (killIdx > defIndex) {
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assert(vi.AliveBlocks.empty() &&
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"Shouldn't be alive across any blocks!");
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LiveRange LR(defIndex, killIdx, ValNum);
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interval.addRange(LR);
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DEBUG(std::cerr << " +" << LR << "\n");
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return;
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}
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}
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// The other case we handle is when a virtual register lives to the end
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// of the defining block, potentially live across some blocks, then is
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// live into some number of blocks, but gets killed. Start by adding a
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// range that goes from this definition to the end of the defining block.
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LiveRange NewLR(defIndex,
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getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
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ValNum);
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DEBUG(std::cerr << " +" << NewLR);
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interval.addRange(NewLR);
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// Iterate over all of the blocks that the variable is completely
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// live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
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// live interval.
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for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
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if (vi.AliveBlocks[i]) {
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MachineBasicBlock* mbb = mf_->getBlockNumbered(i);
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if (!mbb->empty()) {
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LiveRange LR(getInstructionIndex(&mbb->front()),
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getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
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ValNum);
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interval.addRange(LR);
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DEBUG(std::cerr << " +" << LR);
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}
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}
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}
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// Finally, this virtual register is live from the start of any killing
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// block to the 'use' slot of the killing instruction.
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for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
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MachineInstr *Kill = vi.Kills[i];
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LiveRange LR(getInstructionIndex(Kill->getParent()->begin()),
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getUseIndex(getInstructionIndex(Kill))+1,
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ValNum);
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interval.addRange(LR);
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DEBUG(std::cerr << " +" << LR);
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}
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} else {
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// If this is the second time we see a virtual register definition, it
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// must be due to phi elimination or two addr elimination. If this is
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// the result of two address elimination, then the vreg is the first
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// operand, and is a def-and-use.
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if (mi->getOperand(0).isRegister() &&
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mi->getOperand(0).getReg() == interval.reg &&
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mi->getOperand(0).isDef() && mi->getOperand(0).isUse()) {
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// If this is a two-address definition, then we have already processed
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// the live range. The only problem is that we didn't realize there
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// are actually two values in the live interval. Because of this we
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// need to take the LiveRegion that defines this register and split it
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// into two values.
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unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
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unsigned RedefIndex = getDefIndex(getInstructionIndex(mi));
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// Delete the initial value, which should be short and continuous,
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// becuase the 2-addr copy must be in the same MBB as the redef.
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interval.removeRange(DefIndex, RedefIndex);
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LiveRange LR(DefIndex, RedefIndex, interval.getNextValue());
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DEBUG(std::cerr << " replace range with " << LR);
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interval.addRange(LR);
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// If this redefinition is dead, we need to add a dummy unit live
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// range covering the def slot.
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for (LiveVariables::killed_iterator KI = lv_->dead_begin(mi),
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E = lv_->dead_end(mi); KI != E; ++KI)
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if (KI->second == interval.reg) {
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interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
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break;
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}
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DEBUG(std::cerr << "RESULT: " << interval);
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} else {
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// Otherwise, this must be because of phi elimination. If this is the
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// first redefinition of the vreg that we have seen, go back and change
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// the live range in the PHI block to be a different value number.
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if (interval.containsOneValue()) {
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assert(vi.Kills.size() == 1 &&
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"PHI elimination vreg should have one kill, the PHI itself!");
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// Remove the old range that we now know has an incorrect number.
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MachineInstr *Killer = vi.Kills[0];
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unsigned Start = getInstructionIndex(Killer->getParent()->begin());
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unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
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DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: "
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<< interval << "\n");
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interval.removeRange(Start, End);
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DEBUG(std::cerr << "RESULT: " << interval);
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// Replace the interval with one of a NEW value number.
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LiveRange LR(Start, End, interval.getNextValue());
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DEBUG(std::cerr << " replace range with " << LR);
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interval.addRange(LR);
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DEBUG(std::cerr << "RESULT: " << interval);
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}
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// In the case of PHI elimination, each variable definition is only
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// live until the end of the block. We've already taken care of the
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// rest of the live range.
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unsigned defIndex = getDefIndex(getInstructionIndex(mi));
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LiveRange LR(defIndex,
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getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
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interval.getNextValue());
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interval.addRange(LR);
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DEBUG(std::cerr << " +" << LR);
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}
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}
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DEBUG(std::cerr << '\n');
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}
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void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator mi,
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LiveInterval& interval)
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{
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// A physical register cannot be live across basic block, so its
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// lifetime must end somewhere in its defining basic block.
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DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
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typedef LiveVariables::killed_iterator KillIter;
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unsigned baseIndex = getInstructionIndex(mi);
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unsigned start = getDefIndex(baseIndex);
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unsigned end = start;
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// If it is not used after definition, it is considered dead at
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// the instruction defining it. Hence its interval is:
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// [defSlot(def), defSlot(def)+1)
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for (KillIter ki = lv_->dead_begin(mi), ke = lv_->dead_end(mi);
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ki != ke; ++ki) {
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if (interval.reg == ki->second) {
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DEBUG(std::cerr << " dead");
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end = getDefIndex(start) + 1;
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goto exit;
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}
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}
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// If it is not dead on definition, it must be killed by a
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// subsequent instruction. Hence its interval is:
|
|
// [defSlot(def), useSlot(kill)+1)
|
|
while (true) {
|
|
++mi;
|
|
assert(mi != MBB->end() && "physreg was not killed in defining block!");
|
|
baseIndex += InstrSlots::NUM;
|
|
for (KillIter ki = lv_->killed_begin(mi), ke = lv_->killed_end(mi);
|
|
ki != ke; ++ki) {
|
|
if (interval.reg == ki->second) {
|
|
DEBUG(std::cerr << " killed");
|
|
end = getUseIndex(baseIndex) + 1;
|
|
goto exit;
|
|
}
|
|
}
|
|
}
|
|
|
|
exit:
|
|
assert(start < end && "did not find end of interval?");
|
|
LiveRange LR(start, end, interval.getNextValue());
|
|
interval.addRange(LR);
|
|
DEBUG(std::cerr << " +" << LR << '\n');
|
|
}
|
|
|
|
void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned reg) {
|
|
if (MRegisterInfo::isVirtualRegister(reg))
|
|
handleVirtualRegisterDef(MBB, MI, getOrCreateInterval(reg));
|
|
else if (allocatableRegs_[reg]) {
|
|
handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(reg));
|
|
for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS)
|
|
handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(*AS));
|
|
}
|
|
}
|
|
|
|
/// computeIntervals - computes the live intervals for virtual
|
|
/// registers. for some ordering of the machine instructions [1,N] a
|
|
/// live interval is an interval [i, j) where 1 <= i <= j < N for
|
|
/// which a variable is live
|
|
void LiveIntervals::computeIntervals()
|
|
{
|
|
DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n");
|
|
DEBUG(std::cerr << "********** Function: "
|
|
<< ((Value*)mf_->getFunction())->getName() << '\n');
|
|
|
|
for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
|
|
I != E; ++I) {
|
|
MachineBasicBlock* mbb = I;
|
|
DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n");
|
|
|
|
for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
|
|
mi != miEnd; ++mi) {
|
|
const TargetInstrDescriptor& tid =
|
|
tm_->getInstrInfo()->get(mi->getOpcode());
|
|
DEBUG(std::cerr << getInstructionIndex(mi) << "\t" << *mi);
|
|
|
|
// handle implicit defs
|
|
for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
|
|
handleRegisterDef(mbb, mi, *id);
|
|
|
|
// handle explicit defs
|
|
for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
|
|
MachineOperand& mop = mi->getOperand(i);
|
|
// handle register defs - build intervals
|
|
if (mop.isRegister() && mop.getReg() && mop.isDef())
|
|
handleRegisterDef(mbb, mi, mop.getReg());
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void LiveIntervals::joinIntervalsInMachineBB(MachineBasicBlock *MBB) {
|
|
DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
|
|
const TargetInstrInfo &TII = *tm_->getInstrInfo();
|
|
|
|
for (MachineBasicBlock::iterator mi = MBB->begin(), mie = MBB->end();
|
|
mi != mie; ++mi) {
|
|
DEBUG(std::cerr << getInstructionIndex(mi) << '\t' << *mi);
|
|
|
|
// we only join virtual registers with allocatable
|
|
// physical registers since we do not have liveness information
|
|
// on not allocatable physical registers
|
|
unsigned regA, regB;
|
|
if (TII.isMoveInstr(*mi, regA, regB) &&
|
|
(MRegisterInfo::isVirtualRegister(regA) || allocatableRegs_[regA]) &&
|
|
(MRegisterInfo::isVirtualRegister(regB) || allocatableRegs_[regB])) {
|
|
|
|
// Get representative registers.
|
|
regA = rep(regA);
|
|
regB = rep(regB);
|
|
|
|
// If they are already joined we continue.
|
|
if (regA == regB)
|
|
continue;
|
|
|
|
// If they are both physical registers, we cannot join them.
|
|
if (MRegisterInfo::isPhysicalRegister(regA) &&
|
|
MRegisterInfo::isPhysicalRegister(regB))
|
|
continue;
|
|
|
|
// If they are not of the same register class, we cannot join them.
|
|
if (differingRegisterClasses(regA, regB))
|
|
continue;
|
|
|
|
LiveInterval &IntA = getInterval(regA);
|
|
LiveInterval &IntB = getInterval(regB);
|
|
assert(IntA.reg == regA && IntB.reg == regB &&
|
|
"Register mapping is horribly broken!");
|
|
|
|
DEBUG(std::cerr << "\t\tInspecting " << IntA << " and " << IntB << ": ");
|
|
|
|
// If two intervals contain a single value and are joined by a copy, it
|
|
// does not matter if the intervals overlap, they can always be joined.
|
|
bool TriviallyJoinable =
|
|
IntA.containsOneValue() && IntB.containsOneValue();
|
|
|
|
unsigned MIDefIdx = getDefIndex(getInstructionIndex(mi));
|
|
if ((TriviallyJoinable || IntB.joinable(IntA, MIDefIdx)) &&
|
|
!overlapsAliases(&IntA, &IntB)) {
|
|
IntB.join(IntA, MIDefIdx);
|
|
|
|
if (!MRegisterInfo::isPhysicalRegister(regA)) {
|
|
r2iMap_.erase(regA);
|
|
r2rMap_[regA] = regB;
|
|
} else {
|
|
// Otherwise merge the data structures the other way so we don't lose
|
|
// the physreg information.
|
|
r2rMap_[regB] = regA;
|
|
IntB.reg = regA;
|
|
IntA.swap(IntB);
|
|
r2iMap_.erase(regB);
|
|
}
|
|
DEBUG(std::cerr << "Joined. Result = " << IntB << "\n");
|
|
++numJoins;
|
|
} else {
|
|
DEBUG(std::cerr << "Interference!\n");
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
namespace {
|
|
// DepthMBBCompare - Comparison predicate that sort first based on the loop
|
|
// depth of the basic block (the unsigned), and then on the MBB number.
|
|
struct DepthMBBCompare {
|
|
typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
|
|
bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
|
|
if (LHS.first > RHS.first) return true; // Deeper loops first
|
|
return LHS.first == RHS.first &&
|
|
LHS.second->getNumber() < RHS.second->getNumber();
|
|
}
|
|
};
|
|
}
|
|
|
|
void LiveIntervals::joinIntervals() {
|
|
DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n");
|
|
|
|
const LoopInfo &LI = getAnalysis<LoopInfo>();
|
|
if (LI.begin() == LI.end()) {
|
|
// If there are no loops in the function, join intervals in function order.
|
|
for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
|
|
I != E; ++I)
|
|
joinIntervalsInMachineBB(I);
|
|
} else {
|
|
// Otherwise, join intervals in inner loops before other intervals.
|
|
// Unfortunately we can't just iterate over loop hierarchy here because
|
|
// there may be more MBB's than BB's. Collect MBB's for sorting.
|
|
std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
|
|
for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
|
|
I != E; ++I)
|
|
MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
|
|
|
|
// Sort by loop depth.
|
|
std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
|
|
|
|
// Finally, join intervals in loop nest order.
|
|
for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
|
|
joinIntervalsInMachineBB(MBBs[i].second);
|
|
}
|
|
|
|
DEBUG(std::cerr << "*** Register mapping ***\n");
|
|
DEBUG(for (int i = 0, e = r2rMap_.size(); i != e; ++i)
|
|
if (r2rMap_[i])
|
|
std::cerr << " reg " << i << " -> reg " << r2rMap_[i] << "\n");
|
|
}
|
|
|
|
/// Return true if the two specified registers belong to different register
|
|
/// classes. The registers may be either phys or virt regs.
|
|
bool LiveIntervals::differingRegisterClasses(unsigned RegA,
|
|
unsigned RegB) const {
|
|
|
|
// Get the register classes for the first reg.
|
|
if (MRegisterInfo::isPhysicalRegister(RegA)) {
|
|
assert(MRegisterInfo::isVirtualRegister(RegB) &&
|
|
"Shouldn't consider two physregs!");
|
|
return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
|
|
}
|
|
|
|
// Compare against the regclass for the second reg.
|
|
const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
|
|
if (MRegisterInfo::isVirtualRegister(RegB))
|
|
return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
|
|
else
|
|
return !RegClass->contains(RegB);
|
|
}
|
|
|
|
bool LiveIntervals::overlapsAliases(const LiveInterval *LHS,
|
|
const LiveInterval *RHS) const {
|
|
if (!MRegisterInfo::isPhysicalRegister(LHS->reg)) {
|
|
if (!MRegisterInfo::isPhysicalRegister(RHS->reg))
|
|
return false; // vreg-vreg merge has no aliases!
|
|
std::swap(LHS, RHS);
|
|
}
|
|
|
|
assert(MRegisterInfo::isPhysicalRegister(LHS->reg) &&
|
|
MRegisterInfo::isVirtualRegister(RHS->reg) &&
|
|
"first interval must describe a physical register");
|
|
|
|
for (const unsigned *AS = mri_->getAliasSet(LHS->reg); *AS; ++AS)
|
|
if (RHS->overlaps(getInterval(*AS)))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
LiveInterval LiveIntervals::createInterval(unsigned reg) {
|
|
float Weight = MRegisterInfo::isPhysicalRegister(reg) ? HUGE_VAL :0.0F;
|
|
return LiveInterval(reg, Weight);
|
|
}
|