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cf0b01d7ec
Add the Lanai backend to lib/Target. General Lanai backend discussion on llvm-dev thread "[RFC] Lanai backend" (http://lists.llvm.org/pipermail/llvm-dev/2016-February/095118.html). Differential Revision: http://reviews.llvm.org/D17011 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264578 91177308-0d34-0410-b5e6-96231b3b80d8
127 lines
3.5 KiB
LLVM
127 lines
3.5 KiB
LLVM
; RUN: llc < %s -march=lanai | FileCheck %s
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; Test the alu setcc combiner.
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; TODO: Enhance combiner to handle this case. This expands into:
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; sub %r7, %r6, %r3
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; sub.f %r7, %r6, %r0
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; sel.eq %r18, %r3, %rv
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; This is different from the pattern currently matched. If the lowered form had
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; been sub.f %r3, 0, %r0 then it would have matched.
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; Function Attrs: norecurse nounwind readnone
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define i32 @test0a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) #0 {
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entry:
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%sub = sub i32 %b, %a
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%cmp = icmp eq i32 %sub, 0
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%cond = select i1 %cmp, i32 %c, i32 %sub
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ret i32 %cond
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}
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; CHECK-LABEL: test0a
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; CHECK: sub.f %r7
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; CHECK: sel.eq
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; Function Attrs: norecurse nounwind readnone
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define i32 @test0b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) #0 {
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entry:
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%cmp = icmp eq i32 %b, %a
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%cond = select i1 %cmp, i32 %c, i32 %b
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ret i32 %cond
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}
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; CHECK-LABEL: test0b
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; CHECK: sub.f %r7, %r6, %r0
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; CHECK-NEXT: sel.eq
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; Function Attrs: norecurse nounwind readnone
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define i32 @test1a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) #0 {
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entry:
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%sub = sub i32 %b, %a
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%cmp = icmp slt i32 %sub, 0
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%cond = select i1 %cmp, i32 %c, i32 %d
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ret i32 %cond
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}
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; CHECK-LABEL: test1a
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; CHECK: sub.f %r7, %r6
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; CHECK-NEXT: sel.mi
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; Function Attrs: norecurse nounwind readnone
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define i32 @test1b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) #0 {
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entry:
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%sub = sub i32 %b, %a
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%cmp = icmp slt i32 %sub, 0
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%cond = select i1 %cmp, i32 %c, i32 %d
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ret i32 %cond
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}
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; CHECK-LABEL: test1b
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; CHECK: sub.f %r7, %r6
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; CHECK-NEXT: sel.mi
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; Function Attrs: norecurse nounwind readnone
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define i32 @test2a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) #0 {
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entry:
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%sub = sub i32 %b, %a
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%cmp = icmp sgt i32 %sub, -1
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%cond = select i1 %cmp, i32 %c, i32 %d
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ret i32 %cond
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}
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; CHECK-LABEL: test2a
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; CHECK: sub.f %r7, %r6
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; CHECK: sel.pl
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; Function Attrs: norecurse nounwind readnone
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define i32 @test2b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) #0 {
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entry:
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%sub = sub i32 %b, %a
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%cmp = icmp sgt i32 %sub, -1
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%cond = select i1 %cmp, i32 %c, i32 %d
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ret i32 %cond
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}
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; CHECK-LABEL: test2b
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; CHECK: sub.f %r7, %r6
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; CHECK: sel.pl
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; Function Attrs: norecurse nounwind readnone
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define i32 @test3(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) #0 {
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entry:
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%sub = sub i32 %b, %a
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%cmp = icmp slt i32 %sub, 1
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%cond = select i1 %cmp, i32 %c, i32 %d
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ret i32 %cond
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}
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; Function Attrs: norecurse nounwind readnone
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define i32 @test4(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) #0 {
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entry:
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%cmp = icmp ne i32 %a, 0
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%cmp1 = icmp ult i32 %a, %b
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%or.cond = and i1 %cmp, %cmp1
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br i1 %or.cond, label %return, label %if.end
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if.end: ; preds = %entry
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%cmp2 = icmp ne i32 %b, 0
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%cmp4 = icmp ult i32 %b, %c
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%or.cond29 = and i1 %cmp2, %cmp4
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br i1 %or.cond29, label %return, label %if.end6
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if.end6: ; preds = %if.end
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%cmp7 = icmp ne i32 %c, 0
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%cmp9 = icmp ult i32 %c, %d
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%or.cond30 = and i1 %cmp7, %cmp9
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br i1 %or.cond30, label %return, label %if.end11
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if.end11: ; preds = %if.end6
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%cmp12 = icmp ne i32 %d, 0
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%cmp14 = icmp ult i32 %d, %a
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%or.cond31 = and i1 %cmp12, %cmp14
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%b. = select i1 %or.cond31, i32 %b, i32 21
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ret i32 %b.
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return: ; preds = %if.end6, %if.end, %entry
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%retval.0 = phi i32 [ %c, %entry ], [ %d, %if.end ], [ %a, %if.end6 ]
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ret i32 %retval.0
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}
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; CHECK-LABEL: test4
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; CHECK: and.f
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; CHECK: and.f
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; CHECK: and.f
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