Ahmed Bougacha cbd2ff78c0 [MIRParser] Allow generic register specification on operand. ...

This completes r292321 by adding support for generic registers, e.g.:

  %2:_(s32) = G_ADD %0, %1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292550 91177308-0d34-0410-b5e6-96231b3b80d8

2017-01-20 00:29:59 +00:00

..

CMakeLists.txt

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LLVMBuild.txt

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MILexer.cpp

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MILexer.h

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MIParser.cpp

[MIRParser] Allow generic register specification on operand.

2017-01-20 00:29:59 +00:00

MIParser.h

MIRParser: Allow regclass specification on operand

2017-01-18 00:59:19 +00:00

MIRParser.cpp

MIRParser: Allow regclass specification on operand

2017-01-18 00:59:19 +00:00