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ed541fe200
Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250407 91177308-0d34-0410-b5e6-96231b3b80d8
36 lines
1.4 KiB
LLVM
36 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands < %s | FileCheck %s
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; ModuleID = 'const1.c'
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"
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target triple = "mipsel-unknown-linux"
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@i = common global i32 0, align 4
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@j = common global i32 0, align 4
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@k = common global i32 0, align 4
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@l = common global i32 0, align 4
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; Function Attrs: nounwind
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define void @t() #0 {
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entry:
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store i32 -559023410, i32* @i, align 4
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store i32 -559023410, i32* @j, align 4
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store i32 -87105875, i32* @k, align 4
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store i32 262991277, i32* @l, align 4
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ret void
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; CHECK: lw ${{[0-9]+}}, $CPI0_0
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; CHECK: lw ${{[0-9]+}}, $CPI0_1
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; CHECK: lw ${{[0-9]+}}, $CPI0_2
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; CHECK: $CPI0_0:
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; CHECK: .4byte 3735943886
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; CHECK: $CPI0_1:
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; CHECK: .4byte 4207861421
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; CHECK: $CPI0_2:
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; CHECK: .4byte 262991277
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" }
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!llvm.ident = !{!0}
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!0 = !{!"clang version 3.4 (gitosis@dmz-portal.mips.com:clang.git b754974ec32ab712ea7d8b52cd8037b24e7d6ed3) (gitosis@dmz-portal.mips.com:llvm.git 8e211187b501bc73edb938fde0019c9a20bcffd5)"}
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