Simon Pilgrim d2d5b99bae [X86] Add knownbits vector SUB test ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286508 91177308-0d34-0410-b5e6-96231b3b80d8		2016-11-10 21:50:23 +00:00
..
AArch64	RegisterCoalescer: Ignore interferences for constant physregs	2016-11-10 21:22:47 +00:00
AMDGPU	AMDGPU: Emit runtime metadata as a note element in .note section	2016-11-10 21:18:49 +00:00
ARM	[Thumb1] Move padding earlier when synthesizing TBBs off of the PC	2016-11-07 13:38:21 +00:00
AVR	[AVR] Add a selection of CodeGen tests	2016-11-09 23:46:52 +00:00
BPF
Generic	Add -O0 support for @llvm.invariant.group.barrier by discarding it if it gets to ISel.	2016-11-07 16:47:20 +00:00
Hexagon	[Hexagon] Separate Hexagon subreg indices for different register classes	2016-11-09 16:19:08 +00:00
Inputs
Lanai
Mips	[mips] Renable small data section test.	2016-11-08 13:03:45 +00:00
MIR	AMDGPU: Preserve vcc undef flags when inverting branch	2016-11-07 19:09:27 +00:00
MSP430	Fix PR27500: on MSP430 the branch destination offset is measured in words, not bytes.	2016-11-08 17:19:59 +00:00
NVPTX	[NVPTX] Remove NVPTXFavorNonGenericAddrSpaces pass.	2016-10-31 21:51:42 +00:00
PowerPC	[PowerPC] Implement vector shift builtins - llvm portion	2016-11-01 09:42:32 +00:00
SPARC	[Sparc][LEON] Test for FixFDIVSQRT erratum fix.	2016-11-01 14:23:37 +00:00
SystemZ
Thumb	Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently"	2016-11-03 14:08:01 +00:00
Thumb2	Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently"	2016-11-03 14:08:01 +00:00
WebAssembly	[WebAssembly] Convert stackified IMPLICIT_DEF into constant 0.	2016-11-08 19:40:38 +00:00
WinEH
X86	[X86] Add knownbits vector SUB test	2016-11-10 21:50:23 +00:00
XCore