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47c6d17b1c
Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend. Differential Revision: http://llvm-reviews.chandlerc.com/D2036 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193599 91177308-0d34-0410-b5e6-96231b3b80d8
31 lines
1.5 KiB
ArmAsm
31 lines
1.5 KiB
ArmAsm
@ RUN: llvm-mc -triple=armv8 -show-encoding < %s | FileCheck %s
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@ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
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@ RUN: not llvm-mc -triple=thumbv8 -mattr=-crc -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOCRC
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crc32b r0, r1, r2
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crc32h r0, r1, r2
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crc32w r0, r1, r2
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@ CHECK: crc32b r0, r1, r2 @ encoding: [0x42,0x00,0x01,0xe1]
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@ CHECK: crc32h r0, r1, r2 @ encoding: [0x42,0x00,0x21,0xe1]
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@ CHECK: crc32w r0, r1, r2 @ encoding: [0x42,0x00,0x41,0xe1]
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@ CHECK-V7: error: instruction requires: crc armv8
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@ CHECK-V7: error: instruction requires: crc armv8
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@ CHECK-V7: error: instruction requires: crc armv8
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@ CHECK-NOCRC: error: instruction requires: crc
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@ CHECK-NOCRC: error: instruction requires: crc
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@ CHECK-NOCRC: error: instruction requires: crc
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crc32cb r0, r1, r2
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crc32ch r0, r1, r2
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crc32cw r0, r1, r2
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@ CHECK: crc32cb r0, r1, r2 @ encoding: [0x42,0x02,0x01,0xe1]
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@ CHECK: crc32ch r0, r1, r2 @ encoding: [0x42,0x02,0x21,0xe1]
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@ CHECK: crc32cw r0, r1, r2 @ encoding: [0x42,0x02,0x41,0xe1]
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@ CHECK-V7: error: instruction requires: crc armv8
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@ CHECK-V7: error: instruction requires: crc armv8
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@ CHECK-V7: error: instruction requires: crc armv8
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@ CHECK-NOCRC: error: instruction requires: crc
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@ CHECK-NOCRC: error: instruction requires: crc
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@ CHECK-NOCRC: error: instruction requires: crc
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