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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
50 lines
2.5 KiB
LLVM
50 lines
2.5 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs
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; RUN: llc < %s -verify-machineinstrs -O0
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; PR12177
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;
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; This test case spills a QQQQ register.
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;
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
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target triple = "armv7-none-linux-gnueabi"
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%0 = type { %1*, i32, i32, i32, i8 }
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%1 = type { i32 (...)** }
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%2 = type { i8*, i8*, i8*, i32 }
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%3 = type { %4 }
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%4 = type { i32 (...)**, %2, %4*, i8, i8 }
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declare arm_aapcs_vfpcc void @func1(%0*, float* nocapture, float* nocapture, %2*) nounwind
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declare arm_aapcs_vfpcc %0** @func2()
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declare arm_aapcs_vfpcc %2* @func3(%2*, %2*, i32)
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declare arm_aapcs_vfpcc %2** @func4()
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define arm_aapcs_vfpcc void @foo(%3* nocapture) nounwind align 2 {
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call void @llvm.arm.neon.vst4.v4i32(i8* undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind
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%2 = call arm_aapcs_vfpcc %0** @func2() nounwind
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%3 = load %0*, %0** %2, align 4
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store float 0.000000e+00, float* undef, align 4
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%4 = call arm_aapcs_vfpcc %2* @func3(%2* undef, %2* undef, i32 2956) nounwind
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call arm_aapcs_vfpcc void @func1(%0* %3, float* undef, float* undef, %2* undef)
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%5 = call arm_aapcs_vfpcc %0** @func2() nounwind
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store float 1.000000e+00, float* undef, align 4
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call arm_aapcs_vfpcc void @func1(%0* undef, float* undef, float* undef, %2* undef)
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store float 1.500000e+01, float* undef, align 4
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%6 = call arm_aapcs_vfpcc %2** @func4() nounwind
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%7 = call arm_aapcs_vfpcc %2* @func3(%2* undef, %2* undef, i32 2971) nounwind
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%8 = fadd float undef, -1.000000e+05
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store float %8, float* undef, align 16
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%9 = call arm_aapcs_vfpcc i32 @rand() nounwind
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%10 = fmul float undef, 2.000000e+05
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%11 = fadd float %10, -1.000000e+05
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store float %11, float* undef, align 4
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call void @llvm.arm.neon.vst4.v4i32(i8* undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind
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ret void
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}
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declare void @llvm.arm.neon.vst4.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind
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declare arm_aapcs_vfpcc i32 @rand()
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