Bradley Smith d87c77c0e8 [AArch64] Allow non-standard INS/DUP encodings ... The ARMv8 ARMARM states that for these instructions in A64 state: "Unspecified bits in "imm5" are ignored but should be set to zero by an assembler.", (imm4 for INS). Make the disassembler accept any encoding with these ignored bits set to 1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234896 91177308-0d34-0410-b5e6-96231b3b80d8		2015-04-14 15:07:26 +00:00
..
AArch64	AArch64: disallow "fmov sD, #-0.0" during assembly.	2015-04-07 22:49:47 +00:00
ARM	Write the section header in the end.	2015-04-08 11:41:24 +00:00
AsmParser	Add support for .ifnes psuedo-op.	2015-03-18 14:20:54 +00:00
COFF	[opaque pointer type] Add textual IR support for explicit type parameter to gep operator	2015-03-13 18:20:45 +00:00
Disassembler	[AArch64] Allow non-standard INS/DUP encodings	2015-04-14 15:07:26 +00:00
ELF	Write the section header in the end.	2015-04-08 11:41:24 +00:00
Hexagon	Expand MUX instructions early on Hexagon	2015-03-31 13:35:12 +00:00
MachO	MC: For variable symbols, maintain MCSymbol::Section as a cache.	2015-04-03 01:46:11 +00:00
Markup
Mips	Re-enable target-specific relocation table sorting and use it for Mips	2015-04-14 13:23:34 +00:00
PowerPC	Add direct moves to/from VSR and exploit them for FP/INT conversions	2015-04-11 10:40:42 +00:00
R600	R600/SI: Initial support for assembler and inline assembly	2015-04-08 01:09:26 +00:00
Sparc
SystemZ	[SystemZ] Support transactional execution on zEC12	2015-04-01 12:51:43 +00:00
X86	[MC] Write padding into fragments when -mc-relax-all flag is used	2015-04-12 23:42:25 +00:00