llvm/test/CodeGen
Owen Anderson d966817f3c Add support for code generation of the one register with immediate form of vorr.
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 22:44:51 +00:00
..
Alpha
ARM Add support for code generation of the one register with immediate form of vorr. 2010-11-03 22:44:51 +00:00
Blackfin
CBackend
CellSPU Change v64 datalayout in SPU. 2010-10-26 10:45:47 +00:00
CPP
Generic
MBlaze Recommit 116986 with capitalization typo fixed. 2010-10-21 03:57:26 +00:00
Mips
MSP430 Inline asm mult-alt constraint tests. 2010-11-02 23:01:44 +00:00
PowerPC Inline asm mult-alt constraint tests. 2010-11-02 23:01:44 +00:00
PTX Add test case mov.ll for PTX device function 2010-10-19 13:21:51 +00:00
SPARC Inline asm mult-alt constraint tests. 2010-11-02 23:01:44 +00:00
SystemZ
Thumb Overhaul memory barriers in the ARM backend. Radar 8601999. 2010-10-30 00:54:37 +00:00
Thumb2 Two sets of changes. Sorry they are intermingled. 2010-11-03 00:45:17 +00:00
X86 This test assumes SSE is present; that is not the default 2010-11-03 18:08:41 +00:00
XCore
thumb2-mul.ll Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes 2010-09-21 22:51:46 +00:00