Tim Northover 291cd09645 ARM64: make sure FastISel emits SSA MachineInstrs ... We need to use a temporary register for a 2-step operation like REM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208297 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-08 10:30:56 +00:00
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AArch64	AArch64/ARM64: optimise vector selects & enable test	2014-05-07 14:10:27 +00:00
ARM	Allow using normal .eh_frame based unwinding on ARM. Use the same	2014-05-07 07:49:34 +00:00
ARM64	ARM64: make sure FastISel emits SSA MachineInstrs	2014-05-08 10:30:56 +00:00
CPP
Generic	MC: move test from Generic to COFF	2014-04-23 21:41:07 +00:00
Hexagon
Inputs
Mips	Add basic functionality for assignment of ints.	2014-05-01 20:39:21 +00:00
MSP430
NVPTX	Fix the test: DCE optimized away everything.	2014-04-21 17:23:12 +00:00
PowerPC
R600	R600: Expand i64 ISD:SUB	2014-05-05 21:47:15 +00:00
SPARC	Remove the -disable-cfi option.	2014-05-05 17:33:26 +00:00
SystemZ
Thumb
Thumb2
X86	Lower certain build_vectors to insertps instructions	2014-05-08 00:25:16 +00:00
XCore	Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl"	2014-04-21 17:57:07 +00:00