Evan Cheng 3749943648 Teach liveintervalanalysis about virtual registers which are defined by reg_sequence instructions that are formed by registers defined by distinct instructions. e.g. ... 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0 . . . 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103102 91177308-0d34-0410-b5e6-96231b3b80d8		2010-05-05 18:27:40 +00:00
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llvm	Teach liveintervalanalysis about virtual registers which are defined by reg_sequence instructions that are formed by registers defined by distinct instructions. e.g.	2010-05-05 18:27:40 +00:00
llvm-c	add some more (void)'s to prototypes for PR6961	2010-04-29 23:27:32 +00:00