Tom Stellard df4626ef15 R600/SI: Assign a register class to the $vaddr operand for MIMG instructions ... The previous code declared the operand as unknown:$vaddr, which made it possible for scalar registers to be used instead of vector registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188425 91177308-0d34-0410-b5e6-96231b3b80d8		2013-08-14 23:24:17 +00:00
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AArch64	CHECK-LABEL-ify tests	2013-08-09 17:50:15 +00:00
ARM	Let t2LDRBi8 and t2LDRBi12 have same Base Pointer	2013-08-14 16:35:29 +00:00
CPP	test commit: remove blank line.	2013-03-14 05:43:59 +00:00
Generic	Debug Info: clean up usage of Verify.	2013-06-28 05:43:10 +00:00
Hexagon	Refactor isInTailCallPosition handling	2013-08-06 09:12:35 +00:00
Inputs	Debug Info Verifier: verify SPs in llvm.dbg.sp.	2013-07-27 01:26:08 +00:00
Mips	[mips] Properly parse registers that appear in inline-asm constraints.	2013-08-14 00:21:25 +00:00
MSP430	Use conventional syntax for branches.	2013-07-14 18:19:44 +00:00
NVPTX	[NVPTX] Add missing patterns for i1 [s,u]int_to_fp	2013-08-06 14:13:34 +00:00
PowerPC	Actually fix PPC64 64-bit GPR inline asm constraint matching	2013-08-14 20:05:04 +00:00
R600	R600/SI: Assign a register class to the $vaddr operand for MIMG instructions	2013-08-14 23:24:17 +00:00
SI	Add R600 backend	2012-12-11 21:25:42 +00:00
SPARC	Allocate local registers in order for optimal coloring.	2013-07-25 18:35:14 +00:00
SystemZ	[SystemZ] Use CLC and IPM to implement memcmp	2013-08-12 10:28:10 +00:00
Thumb	Debug Info: update testing cases to pass verifier.	2013-07-29 18:12:58 +00:00
Thumb2	Refactor AnalyzeBranch on ARM. The previous version did not always analyze	2013-07-19 23:52:47 +00:00
X86	llvm/test/CodeGen/X86/setcc-sentinals.ll: Relax expressions for x86_64-win32.	2013-08-14 00:46:00 +00:00
XCore	XCore target: Fix Vararg handling	2013-08-01 08:29:44 +00:00