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e24d66f525
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111974 91177308-0d34-0410-b5e6-96231b3b80d8
452 lines
17 KiB
C++
452 lines
17 KiB
C++
//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the ARM-specific support for the FastISel class. Some
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// of the target-specific code is generated by tablegen in the file
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// ARMGenFastISel.inc, which is #included here.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMRegisterInfo.h"
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#include "ARMTargetMachine.h"
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#include "ARMSubtarget.h"
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#include "llvm/CallingConv.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/GlobalVariable.h"
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#include "llvm/Instructions.h"
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#include "llvm/IntrinsicInst.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CallSite.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/GetElementPtrTypeIterator.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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static cl::opt<bool>
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EnableARMFastISel("arm-fast-isel",
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cl::desc("Turn on experimental ARM fast-isel support"),
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cl::init(false), cl::Hidden);
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namespace {
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class ARMFastISel : public FastISel {
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/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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const ARMSubtarget *Subtarget;
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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const TargetLowering &TLI;
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const ARMFunctionInfo *AFI;
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// FIXME: Remove this and replace it with queries.
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const TargetRegisterClass *FixedRC;
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public:
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explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
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: FastISel(funcInfo),
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TM(funcInfo.MF->getTarget()),
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TII(*TM.getInstrInfo()),
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TLI(*TM.getTargetLowering()) {
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Subtarget = &TM.getSubtarget<ARMSubtarget>();
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AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
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FixedRC = ARM::GPRRegisterClass;
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}
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// Code from FastISel.cpp.
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virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC);
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virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill);
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virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill);
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virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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uint64_t Imm);
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virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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const ConstantFP *FPImm);
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virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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uint64_t Imm);
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virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill,
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uint64_t Imm);
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virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
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unsigned Op0, bool Op0IsKill,
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uint32_t Idx);
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// Backend specific FastISel code.
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virtual bool TargetSelectInstruction(const Instruction *I);
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#include "ARMGenFastISel.inc"
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// Instruction selection routines.
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virtual bool ARMSelectLoad(const Instruction *I);
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// Utility routines.
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private:
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bool ARMLoadAlloca(const Instruction *I);
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bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
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bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
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const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
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};
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} // end anonymous namespace
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// #include "ARMGenCallingConv.inc"
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// DefinesOptionalPredicate - This is different from DefinesPredicate in that
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// we don't care about implicit defs here, just places we'll need to add a
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// default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
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bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
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const TargetInstrDesc &TID = MI->getDesc();
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if (!TID.hasOptionalDef())
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return false;
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// Look to see if our OptionalDef is defining CPSR or CCR.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isDef()) continue;
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if (MO.getReg() == ARM::CPSR)
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*CPSR = true;
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}
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return true;
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}
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// If the machine is predicable go ahead and add the predicate operands, if
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// it needs default CC operands add those.
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const MachineInstrBuilder &
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ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
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MachineInstr *MI = &*MIB;
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// Do we use a predicate?
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if (TII.isPredicable(MI))
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AddDefaultPred(MIB);
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// Do we optionally set a predicate? Preds is size > 0 iff the predicate
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// defines CPSR. All other OptionalDefines in ARM are the CCR register.
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bool CPSR = false;
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if (DefinesOptionalPredicate(MI, &CPSR)) {
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if (CPSR)
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AddDefaultT1CC(MIB);
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else
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AddDefaultCC(MIB);
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}
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return MIB;
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}
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unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
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const TargetRegisterClass* RC) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
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return ResultReg;
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}
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unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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if (II.getNumDefs() >= 1)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
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.addReg(Op0, Op0IsKill * RegState::Kill));
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else {
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addReg(Op0, Op0IsKill * RegState::Kill));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(II.ImplicitDefs[0]));
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}
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return ResultReg;
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}
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unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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if (II.getNumDefs() >= 1)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addReg(Op1, Op1IsKill * RegState::Kill));
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else {
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addReg(Op1, Op1IsKill * RegState::Kill));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(II.ImplicitDefs[0]));
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}
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return ResultReg;
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}
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unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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uint64_t Imm) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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if (II.getNumDefs() >= 1)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addImm(Imm));
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else {
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addImm(Imm));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(II.ImplicitDefs[0]));
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}
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return ResultReg;
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}
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unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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const ConstantFP *FPImm) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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if (II.getNumDefs() >= 1)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addFPImm(FPImm));
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else {
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addFPImm(FPImm));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(II.ImplicitDefs[0]));
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}
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return ResultReg;
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}
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unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill,
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uint64_t Imm) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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if (II.getNumDefs() >= 1)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addReg(Op1, Op1IsKill * RegState::Kill)
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.addImm(Imm));
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else {
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addReg(Op1, Op1IsKill * RegState::Kill)
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.addImm(Imm));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(II.ImplicitDefs[0]));
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}
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return ResultReg;
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}
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unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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uint64_t Imm) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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if (II.getNumDefs() >= 1)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
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.addImm(Imm));
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else {
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addImm(Imm));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(II.ImplicitDefs[0]));
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}
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return ResultReg;
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}
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unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
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unsigned Op0, bool Op0IsKill,
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uint32_t Idx) {
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unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
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assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
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"Cannot yet extract from physregs");
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
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DL, TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(Op0, getKillRegState(Op0IsKill), Idx));
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return ResultReg;
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}
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// Computes the Reg+Offset to get to an object.
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bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
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int &Offset) {
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// Some boilerplate from the X86 FastISel.
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const User *U = NULL;
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unsigned Opcode = Instruction::UserOp1;
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if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
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// Don't walk into other basic blocks; it's possible we haven't
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// visited them yet, so the instructions may not yet be assigned
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// virtual registers.
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if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
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return false;
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Opcode = I->getOpcode();
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U = I;
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} else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
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Opcode = C->getOpcode();
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U = C;
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}
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if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
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if (Ty->getAddressSpace() > 255)
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// Fast instruction selection doesn't support the special
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// address spaces.
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return false;
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switch (Opcode) {
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default:
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//errs() << "Failing Opcode is: " << *Op1 << "\n";
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break;
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case Instruction::Alloca: {
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assert(false && "Alloca should have been handled earlier!");
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return false;
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}
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}
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if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
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//errs() << "Failing GV is: " << GV << "\n";
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(void)GV;
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return false;
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}
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// Try to get this in a register if nothing else has worked.
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Reg = getRegForValue(Obj);
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return Reg != 0;
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}
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bool ARMFastISel::ARMLoadAlloca(const Instruction *I) {
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Value *Op0 = I->getOperand(0);
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// Verify it's an alloca.
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if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) {
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DenseMap<const AllocaInst*, int>::iterator SI =
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FuncInfo.StaticAllocaMap.find(AI);
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if (SI != FuncInfo.StaticAllocaMap.end()) {
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unsigned ResultReg = createResultReg(FixedRC);
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TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
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ResultReg, SI->second, FixedRC,
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TM.getRegisterInfo());
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UpdateValueMap(I, ResultReg);
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return true;
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}
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}
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return false;
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}
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bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
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// Our register and offset with innocuous defaults.
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unsigned Reg = 0;
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int Offset = 0;
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// If we're an alloca we know we have a frame index and can emit the load
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// directly in short order.
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if (ARMLoadAlloca(I))
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return true;
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// See if we can handle this as Reg + Offset
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if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
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return false;
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// Since the offset may be too large for the load instruction
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// get the reg+offset into a register.
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// TODO: Optimize this somewhat.
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ARMCC::CondCodes Pred = ARMCC::AL;
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unsigned PredReg = 0;
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if (!AFI->isThumbFunction())
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emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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Reg, Reg, Offset, Pred, PredReg,
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static_cast<const ARMBaseInstrInfo&>(TII));
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else {
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assert(AFI->isThumb2Function());
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emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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Reg, Reg, Offset, Pred, PredReg,
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static_cast<const ARMBaseInstrInfo&>(TII));
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}
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// FIXME: There is more than one register class in the world...
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// TODO: Verify the additions above work, otherwise we'll need to add the
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// offset instead of 0 and do all sorts of operand munging.
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unsigned ResultReg = createResultReg(FixedRC);
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// TODO: Fix the Addressing modes so that these can share some code.
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if (AFI->isThumb2Function())
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(ARM::tLDR), ResultReg)
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.addReg(Reg).addImm(0).addReg(0));
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else
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(ARM::LDR), ResultReg)
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.addReg(Reg).addReg(0).addImm(0));
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UpdateValueMap(I, ResultReg);
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return true;
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}
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bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
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// No Thumb-1 for now.
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if (AFI->isThumbFunction() && !AFI->isThumb2Function()) return false;
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switch (I->getOpcode()) {
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case Instruction::Load:
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return ARMSelectLoad(I);
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default: break;
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}
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return false;
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}
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namespace llvm {
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llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
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if (EnableARMFastISel) return new ARMFastISel(funcInfo);
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return 0;
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}
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}
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