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cc3830e7da
Summary: Some targets need to be able to do more complex rendering than just adding an operand or two to an instruction. For example, it may need to insert an instruction to extract a subreg first, or it may need to perform an operation on the operand. In SelectionDAG, targets would create SDNode's to achieve the desired effect during the complex pattern predicate. This worked because SelectionDAG had a form of garbage collection that would take care of SDNode's that were created but not used due to a later predicate rejecting a match. This doesn't translate well to GlobalISel and the churn was wasteful. The API changes in this patch enable GlobalISel to accomplish the same thing without the waste. The API is now: InstructionSelector::OptionalComplexRendererFn selectArithImmed(MachineOperand &Root) const; where Root is the root of the match. The return value can be omitted to indicate that the predicate failed to match, or a function with the signature ComplexRendererFn can be returned. For example: return OptionalComplexRendererFn( [=](MachineInstrBuilder &MIB) { MIB.addImm(Immed).addImm(ShVal); }); adds two immediate operands to the rendered instruction. Immed and ShVal are captured from the predicate function. As an added bonus, this also reduces the amount of information we need to provide to GIComplexOperandMatcher. Depends on D31418 Reviewers: aditya_nandakumar, t.p.northover, qcolombet, rovka, ab, javed.absar Reviewed By: ab Subscribers: dberris, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31761 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301079 91177308-0d34-0410-b5e6-96231b3b80d8
1080 lines
35 KiB
C++
1080 lines
35 KiB
C++
//===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the class that prints out the LLVM IR and machine
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// functions using the MIR serialization format.
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//
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//===----------------------------------------------------------------------===//
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#include "MIRPrinter.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallBitVector.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/MIRYamlMapping.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DebugInfo.h"
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#include "llvm/IR/IRPrintingPasses.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/Module.h"
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#include "llvm/IR/ModuleSlotTracker.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/MemoryBuffer.h"
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#include "llvm/Support/YAMLTraits.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetIntrinsicInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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namespace {
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/// This structure describes how to print out stack object references.
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struct FrameIndexOperand {
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std::string Name;
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unsigned ID;
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bool IsFixed;
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FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
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: Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
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/// Return an ordinary stack object reference.
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static FrameIndexOperand create(StringRef Name, unsigned ID) {
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return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
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}
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/// Return a fixed stack object reference.
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static FrameIndexOperand createFixed(unsigned ID) {
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return FrameIndexOperand("", ID, /*IsFixed=*/true);
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}
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};
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} // end anonymous namespace
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namespace llvm {
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/// This class prints out the machine functions using the MIR serialization
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/// format.
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class MIRPrinter {
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raw_ostream &OS;
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DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
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/// Maps from stack object indices to operand indices which will be used when
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/// printing frame index machine operands.
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DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
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public:
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MIRPrinter(raw_ostream &OS) : OS(OS) {}
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void print(const MachineFunction &MF);
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void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
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const TargetRegisterInfo *TRI);
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void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
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const MachineFrameInfo &MFI);
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void convert(yaml::MachineFunction &MF,
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const MachineConstantPool &ConstantPool);
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void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
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const MachineJumpTableInfo &JTI);
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void convertStackObjects(yaml::MachineFunction &YMF,
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const MachineFunction &MF, ModuleSlotTracker &MST);
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private:
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void initRegisterMaskIds(const MachineFunction &MF);
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};
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/// This class prints out the machine instructions using the MIR serialization
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/// format.
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class MIPrinter {
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raw_ostream &OS;
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ModuleSlotTracker &MST;
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const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
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const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
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public:
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MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
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const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
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const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
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: OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
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StackObjectOperandMapping(StackObjectOperandMapping) {}
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void print(const MachineBasicBlock &MBB);
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void print(const MachineInstr &MI);
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void printMBBReference(const MachineBasicBlock &MBB);
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void printIRBlockReference(const BasicBlock &BB);
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void printIRValueReference(const Value &V);
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void printStackObjectReference(int FrameIndex);
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void printOffset(int64_t Offset);
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void printTargetFlags(const MachineOperand &Op);
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void print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
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unsigned I, bool ShouldPrintRegisterTies,
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LLT TypeToPrint, bool IsDef = false);
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void print(const MachineMemOperand &Op);
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void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
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};
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} // end namespace llvm
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namespace llvm {
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namespace yaml {
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/// This struct serializes the LLVM IR module.
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template <> struct BlockScalarTraits<Module> {
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static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
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Mod.print(OS, nullptr);
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}
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static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
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llvm_unreachable("LLVM Module is supposed to be parsed separately");
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return "";
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}
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};
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} // end namespace yaml
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} // end namespace llvm
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static void printReg(unsigned Reg, raw_ostream &OS,
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const TargetRegisterInfo *TRI) {
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// TODO: Print Stack Slots.
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if (!Reg)
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OS << '_';
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else if (TargetRegisterInfo::isVirtualRegister(Reg))
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OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
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else if (Reg < TRI->getNumRegs())
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OS << '%' << StringRef(TRI->getName(Reg)).lower();
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else
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llvm_unreachable("Can't print this kind of register yet");
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}
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static void printReg(unsigned Reg, yaml::StringValue &Dest,
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const TargetRegisterInfo *TRI) {
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raw_string_ostream OS(Dest.Value);
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printReg(Reg, OS, TRI);
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}
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void MIRPrinter::print(const MachineFunction &MF) {
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initRegisterMaskIds(MF);
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yaml::MachineFunction YamlMF;
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YamlMF.Name = MF.getName();
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YamlMF.Alignment = MF.getAlignment();
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YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
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YamlMF.NoVRegs = MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::NoVRegs);
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YamlMF.Legalized = MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::Legalized);
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YamlMF.RegBankSelected = MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::RegBankSelected);
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YamlMF.Selected = MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::Selected);
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convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
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ModuleSlotTracker MST(MF.getFunction()->getParent());
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MST.incorporateFunction(*MF.getFunction());
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convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
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convertStackObjects(YamlMF, MF, MST);
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if (const auto *ConstantPool = MF.getConstantPool())
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convert(YamlMF, *ConstantPool);
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if (const auto *JumpTableInfo = MF.getJumpTableInfo())
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convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
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raw_string_ostream StrOS(YamlMF.Body.Value.Value);
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bool IsNewlineNeeded = false;
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for (const auto &MBB : MF) {
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if (IsNewlineNeeded)
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StrOS << "\n";
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MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
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.print(MBB);
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IsNewlineNeeded = true;
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}
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StrOS.flush();
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yaml::Output Out(OS);
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Out << YamlMF;
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}
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static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
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const TargetRegisterInfo *TRI) {
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assert(RegMask && "Can't print an empty register mask");
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OS << StringRef("CustomRegMask(");
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bool IsRegInRegMaskFound = false;
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for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
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// Check whether the register is asserted in regmask.
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if (RegMask[I / 32] & (1u << (I % 32))) {
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if (IsRegInRegMaskFound)
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OS << ',';
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printReg(I, OS, TRI);
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IsRegInRegMaskFound = true;
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}
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}
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OS << ')';
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}
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void MIRPrinter::convert(yaml::MachineFunction &MF,
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const MachineRegisterInfo &RegInfo,
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const TargetRegisterInfo *TRI) {
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MF.TracksRegLiveness = RegInfo.tracksLiveness();
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// Print the virtual register definitions.
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for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
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yaml::VirtualRegisterDefinition VReg;
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VReg.ID = I;
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if (RegInfo.getRegClassOrNull(Reg))
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VReg.Class =
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StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
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else if (RegInfo.getRegBankOrNull(Reg))
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VReg.Class = StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
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else {
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VReg.Class = std::string("_");
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assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
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"Generic registers must have a valid type");
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}
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unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
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if (PreferredReg)
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printReg(PreferredReg, VReg.PreferredRegister, TRI);
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MF.VirtualRegisters.push_back(VReg);
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}
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// Print the live ins.
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for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) {
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yaml::MachineFunctionLiveIn LiveIn;
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printReg(I->first, LiveIn.Register, TRI);
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if (I->second)
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printReg(I->second, LiveIn.VirtualRegister, TRI);
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MF.LiveIns.push_back(LiveIn);
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}
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// Prints the callee saved registers.
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if (RegInfo.isUpdatedCSRsInitialized()) {
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const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
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std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
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for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
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yaml::FlowStringValue Reg;
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printReg(*I, Reg, TRI);
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CalleeSavedRegisters.push_back(Reg);
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}
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MF.CalleeSavedRegisters = CalleeSavedRegisters;
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}
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}
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void MIRPrinter::convert(ModuleSlotTracker &MST,
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yaml::MachineFrameInfo &YamlMFI,
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const MachineFrameInfo &MFI) {
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YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
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YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
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YamlMFI.HasStackMap = MFI.hasStackMap();
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YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
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YamlMFI.StackSize = MFI.getStackSize();
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YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
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YamlMFI.MaxAlignment = MFI.getMaxAlignment();
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YamlMFI.AdjustsStack = MFI.adjustsStack();
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YamlMFI.HasCalls = MFI.hasCalls();
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YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
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YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
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YamlMFI.HasVAStart = MFI.hasVAStart();
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YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
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if (MFI.getSavePoint()) {
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raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
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MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
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.printMBBReference(*MFI.getSavePoint());
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}
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if (MFI.getRestorePoint()) {
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raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
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MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
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.printMBBReference(*MFI.getRestorePoint());
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}
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}
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void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
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const MachineFunction &MF,
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ModuleSlotTracker &MST) {
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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// Process fixed stack objects.
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unsigned ID = 0;
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for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
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if (MFI.isDeadObjectIndex(I))
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continue;
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yaml::FixedMachineStackObject YamlObject;
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YamlObject.ID = ID;
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YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
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? yaml::FixedMachineStackObject::SpillSlot
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: yaml::FixedMachineStackObject::DefaultType;
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YamlObject.Offset = MFI.getObjectOffset(I);
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YamlObject.Size = MFI.getObjectSize(I);
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YamlObject.Alignment = MFI.getObjectAlignment(I);
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YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
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YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
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YMF.FixedStackObjects.push_back(YamlObject);
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StackObjectOperandMapping.insert(
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std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
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}
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// Process ordinary stack objects.
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ID = 0;
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for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
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if (MFI.isDeadObjectIndex(I))
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continue;
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yaml::MachineStackObject YamlObject;
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YamlObject.ID = ID;
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if (const auto *Alloca = MFI.getObjectAllocation(I))
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YamlObject.Name.Value =
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Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
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YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
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? yaml::MachineStackObject::SpillSlot
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: MFI.isVariableSizedObjectIndex(I)
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? yaml::MachineStackObject::VariableSized
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: yaml::MachineStackObject::DefaultType;
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YamlObject.Offset = MFI.getObjectOffset(I);
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YamlObject.Size = MFI.getObjectSize(I);
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YamlObject.Alignment = MFI.getObjectAlignment(I);
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YMF.StackObjects.push_back(YamlObject);
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StackObjectOperandMapping.insert(std::make_pair(
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I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
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}
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for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
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yaml::StringValue Reg;
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printReg(CSInfo.getReg(), Reg, TRI);
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auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
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assert(StackObjectInfo != StackObjectOperandMapping.end() &&
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"Invalid stack object index");
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const FrameIndexOperand &StackObject = StackObjectInfo->second;
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if (StackObject.IsFixed)
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YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
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else
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YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
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}
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for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
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auto LocalObject = MFI.getLocalFrameObjectMap(I);
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auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
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assert(StackObjectInfo != StackObjectOperandMapping.end() &&
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"Invalid stack object index");
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const FrameIndexOperand &StackObject = StackObjectInfo->second;
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assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
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YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
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}
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// Print the stack object references in the frame information class after
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// converting the stack objects.
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if (MFI.hasStackProtectorIndex()) {
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raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
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MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
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.printStackObjectReference(MFI.getStackProtectorIndex());
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}
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// Print the debug variable information.
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for (const MachineFunction::VariableDbgInfo &DebugVar :
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MF.getVariableDbgInfo()) {
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auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
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assert(StackObjectInfo != StackObjectOperandMapping.end() &&
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"Invalid stack object index");
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const FrameIndexOperand &StackObject = StackObjectInfo->second;
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assert(!StackObject.IsFixed && "Expected a non-fixed stack object");
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auto &Object = YMF.StackObjects[StackObject.ID];
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{
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raw_string_ostream StrOS(Object.DebugVar.Value);
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DebugVar.Var->printAsOperand(StrOS, MST);
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}
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{
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raw_string_ostream StrOS(Object.DebugExpr.Value);
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DebugVar.Expr->printAsOperand(StrOS, MST);
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}
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{
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raw_string_ostream StrOS(Object.DebugLoc.Value);
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DebugVar.Loc->printAsOperand(StrOS, MST);
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}
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}
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}
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void MIRPrinter::convert(yaml::MachineFunction &MF,
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const MachineConstantPool &ConstantPool) {
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unsigned ID = 0;
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for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
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// TODO: Serialize target specific constant pool entries.
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if (Constant.isMachineConstantPoolEntry())
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llvm_unreachable("Can't print target specific constant pool entries yet");
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yaml::MachineConstantPoolValue YamlConstant;
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std::string Str;
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raw_string_ostream StrOS(Str);
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Constant.Val.ConstVal->printAsOperand(StrOS);
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YamlConstant.ID = ID++;
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YamlConstant.Value = StrOS.str();
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YamlConstant.Alignment = Constant.getAlignment();
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MF.Constants.push_back(YamlConstant);
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}
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}
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void MIRPrinter::convert(ModuleSlotTracker &MST,
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yaml::MachineJumpTable &YamlJTI,
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const MachineJumpTableInfo &JTI) {
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YamlJTI.Kind = JTI.getEntryKind();
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unsigned ID = 0;
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for (const auto &Table : JTI.getJumpTables()) {
|
|
std::string Str;
|
|
yaml::MachineJumpTable::Entry Entry;
|
|
Entry.ID = ID++;
|
|
for (const auto *MBB : Table.MBBs) {
|
|
raw_string_ostream StrOS(Str);
|
|
MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
|
|
.printMBBReference(*MBB);
|
|
Entry.Blocks.push_back(StrOS.str());
|
|
Str.clear();
|
|
}
|
|
YamlJTI.Entries.push_back(Entry);
|
|
}
|
|
}
|
|
|
|
void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
|
|
const auto *TRI = MF.getSubtarget().getRegisterInfo();
|
|
unsigned I = 0;
|
|
for (const uint32_t *Mask : TRI->getRegMasks())
|
|
RegisterMaskIds.insert(std::make_pair(Mask, I++));
|
|
}
|
|
|
|
void MIPrinter::print(const MachineBasicBlock &MBB) {
|
|
assert(MBB.getNumber() >= 0 && "Invalid MBB number");
|
|
OS << "bb." << MBB.getNumber();
|
|
bool HasAttributes = false;
|
|
if (const auto *BB = MBB.getBasicBlock()) {
|
|
if (BB->hasName()) {
|
|
OS << "." << BB->getName();
|
|
} else {
|
|
HasAttributes = true;
|
|
OS << " (";
|
|
int Slot = MST.getLocalSlot(BB);
|
|
if (Slot == -1)
|
|
OS << "<ir-block badref>";
|
|
else
|
|
OS << (Twine("%ir-block.") + Twine(Slot)).str();
|
|
}
|
|
}
|
|
if (MBB.hasAddressTaken()) {
|
|
OS << (HasAttributes ? ", " : " (");
|
|
OS << "address-taken";
|
|
HasAttributes = true;
|
|
}
|
|
if (MBB.isEHPad()) {
|
|
OS << (HasAttributes ? ", " : " (");
|
|
OS << "landing-pad";
|
|
HasAttributes = true;
|
|
}
|
|
if (MBB.getAlignment()) {
|
|
OS << (HasAttributes ? ", " : " (");
|
|
OS << "align " << MBB.getAlignment();
|
|
HasAttributes = true;
|
|
}
|
|
if (HasAttributes)
|
|
OS << ")";
|
|
OS << ":\n";
|
|
|
|
bool HasLineAttributes = false;
|
|
// Print the successors
|
|
if (!MBB.succ_empty()) {
|
|
OS.indent(2) << "successors: ";
|
|
for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
|
|
if (I != MBB.succ_begin())
|
|
OS << ", ";
|
|
printMBBReference(**I);
|
|
if (MBB.hasSuccessorProbabilities())
|
|
OS << '('
|
|
<< format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
|
|
<< ')';
|
|
}
|
|
OS << "\n";
|
|
HasLineAttributes = true;
|
|
}
|
|
|
|
// Print the live in registers.
|
|
const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
|
|
if (MRI.tracksLiveness() && !MBB.livein_empty()) {
|
|
const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
|
|
OS.indent(2) << "liveins: ";
|
|
bool First = true;
|
|
for (const auto &LI : MBB.liveins()) {
|
|
if (!First)
|
|
OS << ", ";
|
|
First = false;
|
|
printReg(LI.PhysReg, OS, &TRI);
|
|
if (!LI.LaneMask.all())
|
|
OS << ":0x" << PrintLaneMask(LI.LaneMask);
|
|
}
|
|
OS << "\n";
|
|
HasLineAttributes = true;
|
|
}
|
|
|
|
if (HasLineAttributes)
|
|
OS << "\n";
|
|
bool IsInBundle = false;
|
|
for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
|
|
const MachineInstr &MI = *I;
|
|
if (IsInBundle && !MI.isInsideBundle()) {
|
|
OS.indent(2) << "}\n";
|
|
IsInBundle = false;
|
|
}
|
|
OS.indent(IsInBundle ? 4 : 2);
|
|
print(MI);
|
|
if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
|
|
OS << " {";
|
|
IsInBundle = true;
|
|
}
|
|
OS << "\n";
|
|
}
|
|
if (IsInBundle)
|
|
OS.indent(2) << "}\n";
|
|
}
|
|
|
|
/// Return true when an instruction has tied register that can't be determined
|
|
/// by the instruction's descriptor.
|
|
static bool hasComplexRegisterTies(const MachineInstr &MI) {
|
|
const MCInstrDesc &MCID = MI.getDesc();
|
|
for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) {
|
|
const auto &Operand = MI.getOperand(I);
|
|
if (!Operand.isReg() || Operand.isDef())
|
|
// Ignore the defined registers as MCID marks only the uses as tied.
|
|
continue;
|
|
int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
|
|
int TiedIdx = Operand.isTied() ? int(MI.findTiedOperandIdx(I)) : -1;
|
|
if (ExpectedTiedIdx != TiedIdx)
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
static LLT getTypeToPrint(const MachineInstr &MI, unsigned OpIdx,
|
|
SmallBitVector &PrintedTypes,
|
|
const MachineRegisterInfo &MRI) {
|
|
const MachineOperand &Op = MI.getOperand(OpIdx);
|
|
if (!Op.isReg())
|
|
return LLT{};
|
|
|
|
if (MI.isVariadic() || OpIdx >= MI.getNumExplicitOperands())
|
|
return MRI.getType(Op.getReg());
|
|
|
|
auto &OpInfo = MI.getDesc().OpInfo[OpIdx];
|
|
if (!OpInfo.isGenericType())
|
|
return MRI.getType(Op.getReg());
|
|
|
|
if (PrintedTypes[OpInfo.getGenericTypeIndex()])
|
|
return LLT{};
|
|
|
|
PrintedTypes.set(OpInfo.getGenericTypeIndex());
|
|
return MRI.getType(Op.getReg());
|
|
}
|
|
|
|
void MIPrinter::print(const MachineInstr &MI) {
|
|
const auto *MF = MI.getParent()->getParent();
|
|
const auto &MRI = MF->getRegInfo();
|
|
const auto &SubTarget = MF->getSubtarget();
|
|
const auto *TRI = SubTarget.getRegisterInfo();
|
|
assert(TRI && "Expected target register info");
|
|
const auto *TII = SubTarget.getInstrInfo();
|
|
assert(TII && "Expected target instruction info");
|
|
if (MI.isCFIInstruction())
|
|
assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
|
|
|
|
SmallBitVector PrintedTypes(8);
|
|
bool ShouldPrintRegisterTies = hasComplexRegisterTies(MI);
|
|
unsigned I = 0, E = MI.getNumOperands();
|
|
for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
|
|
!MI.getOperand(I).isImplicit();
|
|
++I) {
|
|
if (I)
|
|
OS << ", ";
|
|
print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies,
|
|
getTypeToPrint(MI, I, PrintedTypes, MRI),
|
|
/*IsDef=*/true);
|
|
}
|
|
|
|
if (I)
|
|
OS << " = ";
|
|
if (MI.getFlag(MachineInstr::FrameSetup))
|
|
OS << "frame-setup ";
|
|
OS << TII->getName(MI.getOpcode());
|
|
if (I < E)
|
|
OS << ' ';
|
|
|
|
bool NeedComma = false;
|
|
for (; I < E; ++I) {
|
|
if (NeedComma)
|
|
OS << ", ";
|
|
print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies,
|
|
getTypeToPrint(MI, I, PrintedTypes, MRI));
|
|
NeedComma = true;
|
|
}
|
|
|
|
if (MI.getDebugLoc()) {
|
|
if (NeedComma)
|
|
OS << ',';
|
|
OS << " debug-location ";
|
|
MI.getDebugLoc()->printAsOperand(OS, MST);
|
|
}
|
|
|
|
if (!MI.memoperands_empty()) {
|
|
OS << " :: ";
|
|
bool NeedComma = false;
|
|
for (const auto *Op : MI.memoperands()) {
|
|
if (NeedComma)
|
|
OS << ", ";
|
|
print(*Op);
|
|
NeedComma = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
|
|
OS << "%bb." << MBB.getNumber();
|
|
if (const auto *BB = MBB.getBasicBlock()) {
|
|
if (BB->hasName())
|
|
OS << '.' << BB->getName();
|
|
}
|
|
}
|
|
|
|
static void printIRSlotNumber(raw_ostream &OS, int Slot) {
|
|
if (Slot == -1)
|
|
OS << "<badref>";
|
|
else
|
|
OS << Slot;
|
|
}
|
|
|
|
void MIPrinter::printIRBlockReference(const BasicBlock &BB) {
|
|
OS << "%ir-block.";
|
|
if (BB.hasName()) {
|
|
printLLVMNameWithoutPrefix(OS, BB.getName());
|
|
return;
|
|
}
|
|
const Function *F = BB.getParent();
|
|
int Slot;
|
|
if (F == MST.getCurrentFunction()) {
|
|
Slot = MST.getLocalSlot(&BB);
|
|
} else {
|
|
ModuleSlotTracker CustomMST(F->getParent(),
|
|
/*ShouldInitializeAllMetadata=*/false);
|
|
CustomMST.incorporateFunction(*F);
|
|
Slot = CustomMST.getLocalSlot(&BB);
|
|
}
|
|
printIRSlotNumber(OS, Slot);
|
|
}
|
|
|
|
void MIPrinter::printIRValueReference(const Value &V) {
|
|
if (isa<GlobalValue>(V)) {
|
|
V.printAsOperand(OS, /*PrintType=*/false, MST);
|
|
return;
|
|
}
|
|
if (isa<Constant>(V)) {
|
|
// Machine memory operands can load/store to/from constant value pointers.
|
|
OS << '`';
|
|
V.printAsOperand(OS, /*PrintType=*/true, MST);
|
|
OS << '`';
|
|
return;
|
|
}
|
|
OS << "%ir.";
|
|
if (V.hasName()) {
|
|
printLLVMNameWithoutPrefix(OS, V.getName());
|
|
return;
|
|
}
|
|
printIRSlotNumber(OS, MST.getLocalSlot(&V));
|
|
}
|
|
|
|
void MIPrinter::printStackObjectReference(int FrameIndex) {
|
|
auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
|
|
assert(ObjectInfo != StackObjectOperandMapping.end() &&
|
|
"Invalid frame index");
|
|
const FrameIndexOperand &Operand = ObjectInfo->second;
|
|
if (Operand.IsFixed) {
|
|
OS << "%fixed-stack." << Operand.ID;
|
|
return;
|
|
}
|
|
OS << "%stack." << Operand.ID;
|
|
if (!Operand.Name.empty())
|
|
OS << '.' << Operand.Name;
|
|
}
|
|
|
|
void MIPrinter::printOffset(int64_t Offset) {
|
|
if (Offset == 0)
|
|
return;
|
|
if (Offset < 0) {
|
|
OS << " - " << -Offset;
|
|
return;
|
|
}
|
|
OS << " + " << Offset;
|
|
}
|
|
|
|
static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
|
|
auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
|
|
for (const auto &I : Flags) {
|
|
if (I.first == TF) {
|
|
return I.second;
|
|
}
|
|
}
|
|
return nullptr;
|
|
}
|
|
|
|
void MIPrinter::printTargetFlags(const MachineOperand &Op) {
|
|
if (!Op.getTargetFlags())
|
|
return;
|
|
const auto *TII =
|
|
Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo();
|
|
assert(TII && "expected instruction info");
|
|
auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
|
|
OS << "target-flags(";
|
|
const bool HasDirectFlags = Flags.first;
|
|
const bool HasBitmaskFlags = Flags.second;
|
|
if (!HasDirectFlags && !HasBitmaskFlags) {
|
|
OS << "<unknown>) ";
|
|
return;
|
|
}
|
|
if (HasDirectFlags) {
|
|
if (const auto *Name = getTargetFlagName(TII, Flags.first))
|
|
OS << Name;
|
|
else
|
|
OS << "<unknown target flag>";
|
|
}
|
|
if (!HasBitmaskFlags) {
|
|
OS << ") ";
|
|
return;
|
|
}
|
|
bool IsCommaNeeded = HasDirectFlags;
|
|
unsigned BitMask = Flags.second;
|
|
auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
|
|
for (const auto &Mask : BitMasks) {
|
|
// Check if the flag's bitmask has the bits of the current mask set.
|
|
if ((BitMask & Mask.first) == Mask.first) {
|
|
if (IsCommaNeeded)
|
|
OS << ", ";
|
|
IsCommaNeeded = true;
|
|
OS << Mask.second;
|
|
// Clear the bits which were serialized from the flag's bitmask.
|
|
BitMask &= ~(Mask.first);
|
|
}
|
|
}
|
|
if (BitMask) {
|
|
// When the resulting flag's bitmask isn't zero, we know that we didn't
|
|
// serialize all of the bit flags.
|
|
if (IsCommaNeeded)
|
|
OS << ", ";
|
|
OS << "<unknown bitmask target flag>";
|
|
}
|
|
OS << ") ";
|
|
}
|
|
|
|
static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
|
|
const auto *TII = MF.getSubtarget().getInstrInfo();
|
|
assert(TII && "expected instruction info");
|
|
auto Indices = TII->getSerializableTargetIndices();
|
|
for (const auto &I : Indices) {
|
|
if (I.first == Index) {
|
|
return I.second;
|
|
}
|
|
}
|
|
return nullptr;
|
|
}
|
|
|
|
void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
|
|
unsigned I, bool ShouldPrintRegisterTies, LLT TypeToPrint,
|
|
bool IsDef) {
|
|
printTargetFlags(Op);
|
|
switch (Op.getType()) {
|
|
case MachineOperand::MO_Register:
|
|
if (Op.isImplicit())
|
|
OS << (Op.isDef() ? "implicit-def " : "implicit ");
|
|
else if (!IsDef && Op.isDef())
|
|
// Print the 'def' flag only when the operand is defined after '='.
|
|
OS << "def ";
|
|
if (Op.isInternalRead())
|
|
OS << "internal ";
|
|
if (Op.isDead())
|
|
OS << "dead ";
|
|
if (Op.isKill())
|
|
OS << "killed ";
|
|
if (Op.isUndef())
|
|
OS << "undef ";
|
|
if (Op.isEarlyClobber())
|
|
OS << "early-clobber ";
|
|
if (Op.isDebug())
|
|
OS << "debug-use ";
|
|
printReg(Op.getReg(), OS, TRI);
|
|
// Print the sub register.
|
|
if (Op.getSubReg() != 0)
|
|
OS << '.' << TRI->getSubRegIndexName(Op.getSubReg());
|
|
if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
|
|
OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(I) << ")";
|
|
if (TypeToPrint.isValid())
|
|
OS << '(' << TypeToPrint << ')';
|
|
break;
|
|
case MachineOperand::MO_Immediate:
|
|
OS << Op.getImm();
|
|
break;
|
|
case MachineOperand::MO_CImmediate:
|
|
Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
|
|
break;
|
|
case MachineOperand::MO_FPImmediate:
|
|
Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
|
|
break;
|
|
case MachineOperand::MO_MachineBasicBlock:
|
|
printMBBReference(*Op.getMBB());
|
|
break;
|
|
case MachineOperand::MO_FrameIndex:
|
|
printStackObjectReference(Op.getIndex());
|
|
break;
|
|
case MachineOperand::MO_ConstantPoolIndex:
|
|
OS << "%const." << Op.getIndex();
|
|
printOffset(Op.getOffset());
|
|
break;
|
|
case MachineOperand::MO_TargetIndex: {
|
|
OS << "target-index(";
|
|
if (const auto *Name = getTargetIndexName(
|
|
*Op.getParent()->getParent()->getParent(), Op.getIndex()))
|
|
OS << Name;
|
|
else
|
|
OS << "<unknown>";
|
|
OS << ')';
|
|
printOffset(Op.getOffset());
|
|
break;
|
|
}
|
|
case MachineOperand::MO_JumpTableIndex:
|
|
OS << "%jump-table." << Op.getIndex();
|
|
break;
|
|
case MachineOperand::MO_ExternalSymbol:
|
|
OS << '$';
|
|
printLLVMNameWithoutPrefix(OS, Op.getSymbolName());
|
|
printOffset(Op.getOffset());
|
|
break;
|
|
case MachineOperand::MO_GlobalAddress:
|
|
Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
|
|
printOffset(Op.getOffset());
|
|
break;
|
|
case MachineOperand::MO_BlockAddress:
|
|
OS << "blockaddress(";
|
|
Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
|
|
MST);
|
|
OS << ", ";
|
|
printIRBlockReference(*Op.getBlockAddress()->getBasicBlock());
|
|
OS << ')';
|
|
printOffset(Op.getOffset());
|
|
break;
|
|
case MachineOperand::MO_RegisterMask: {
|
|
auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
|
|
if (RegMaskInfo != RegisterMaskIds.end())
|
|
OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
|
|
else
|
|
printCustomRegMask(Op.getRegMask(), OS, TRI);
|
|
break;
|
|
}
|
|
case MachineOperand::MO_RegisterLiveOut: {
|
|
const uint32_t *RegMask = Op.getRegLiveOut();
|
|
OS << "liveout(";
|
|
bool IsCommaNeeded = false;
|
|
for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
|
|
if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
|
|
if (IsCommaNeeded)
|
|
OS << ", ";
|
|
printReg(Reg, OS, TRI);
|
|
IsCommaNeeded = true;
|
|
}
|
|
}
|
|
OS << ")";
|
|
break;
|
|
}
|
|
case MachineOperand::MO_Metadata:
|
|
Op.getMetadata()->printAsOperand(OS, MST);
|
|
break;
|
|
case MachineOperand::MO_MCSymbol:
|
|
OS << "<mcsymbol " << *Op.getMCSymbol() << ">";
|
|
break;
|
|
case MachineOperand::MO_CFIIndex: {
|
|
const MachineFunction &MF = *Op.getParent()->getParent()->getParent();
|
|
print(MF.getFrameInstructions()[Op.getCFIIndex()], TRI);
|
|
break;
|
|
}
|
|
case MachineOperand::MO_IntrinsicID: {
|
|
Intrinsic::ID ID = Op.getIntrinsicID();
|
|
if (ID < Intrinsic::num_intrinsics)
|
|
OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
|
|
else {
|
|
const MachineFunction &MF = *Op.getParent()->getParent()->getParent();
|
|
const TargetIntrinsicInfo *TII = MF.getTarget().getIntrinsicInfo();
|
|
OS << "intrinsic(@" << TII->getName(ID) << ')';
|
|
}
|
|
break;
|
|
}
|
|
case MachineOperand::MO_Predicate: {
|
|
auto Pred = static_cast<CmpInst::Predicate>(Op.getPredicate());
|
|
OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
|
|
<< CmpInst::getPredicateName(Pred) << ')';
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
void MIPrinter::print(const MachineMemOperand &Op) {
|
|
OS << '(';
|
|
// TODO: Print operand's target specific flags.
|
|
if (Op.isVolatile())
|
|
OS << "volatile ";
|
|
if (Op.isNonTemporal())
|
|
OS << "non-temporal ";
|
|
if (Op.isDereferenceable())
|
|
OS << "dereferenceable ";
|
|
if (Op.isInvariant())
|
|
OS << "invariant ";
|
|
if (Op.isLoad())
|
|
OS << "load ";
|
|
else {
|
|
assert(Op.isStore() && "Non load machine operand must be a store");
|
|
OS << "store ";
|
|
}
|
|
|
|
if (Op.getSynchScope() == SynchronizationScope::SingleThread)
|
|
OS << "singlethread ";
|
|
|
|
if (Op.getOrdering() != AtomicOrdering::NotAtomic)
|
|
OS << toIRString(Op.getOrdering()) << ' ';
|
|
if (Op.getFailureOrdering() != AtomicOrdering::NotAtomic)
|
|
OS << toIRString(Op.getFailureOrdering()) << ' ';
|
|
|
|
OS << Op.getSize();
|
|
if (const Value *Val = Op.getValue()) {
|
|
OS << (Op.isLoad() ? " from " : " into ");
|
|
printIRValueReference(*Val);
|
|
} else if (const PseudoSourceValue *PVal = Op.getPseudoValue()) {
|
|
OS << (Op.isLoad() ? " from " : " into ");
|
|
assert(PVal && "Expected a pseudo source value");
|
|
switch (PVal->kind()) {
|
|
case PseudoSourceValue::Stack:
|
|
OS << "stack";
|
|
break;
|
|
case PseudoSourceValue::GOT:
|
|
OS << "got";
|
|
break;
|
|
case PseudoSourceValue::JumpTable:
|
|
OS << "jump-table";
|
|
break;
|
|
case PseudoSourceValue::ConstantPool:
|
|
OS << "constant-pool";
|
|
break;
|
|
case PseudoSourceValue::FixedStack:
|
|
printStackObjectReference(
|
|
cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex());
|
|
break;
|
|
case PseudoSourceValue::GlobalValueCallEntry:
|
|
OS << "call-entry ";
|
|
cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
|
|
OS, /*PrintType=*/false, MST);
|
|
break;
|
|
case PseudoSourceValue::ExternalSymbolCallEntry:
|
|
OS << "call-entry $";
|
|
printLLVMNameWithoutPrefix(
|
|
OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
|
|
break;
|
|
case PseudoSourceValue::TargetCustom:
|
|
llvm_unreachable("TargetCustom pseudo source values are not supported");
|
|
break;
|
|
}
|
|
}
|
|
printOffset(Op.getOffset());
|
|
if (Op.getBaseAlignment() != Op.getSize())
|
|
OS << ", align " << Op.getBaseAlignment();
|
|
auto AAInfo = Op.getAAInfo();
|
|
if (AAInfo.TBAA) {
|
|
OS << ", !tbaa ";
|
|
AAInfo.TBAA->printAsOperand(OS, MST);
|
|
}
|
|
if (AAInfo.Scope) {
|
|
OS << ", !alias.scope ";
|
|
AAInfo.Scope->printAsOperand(OS, MST);
|
|
}
|
|
if (AAInfo.NoAlias) {
|
|
OS << ", !noalias ";
|
|
AAInfo.NoAlias->printAsOperand(OS, MST);
|
|
}
|
|
if (Op.getRanges()) {
|
|
OS << ", !range ";
|
|
Op.getRanges()->printAsOperand(OS, MST);
|
|
}
|
|
OS << ')';
|
|
}
|
|
|
|
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
|
|
const TargetRegisterInfo *TRI) {
|
|
int Reg = TRI->getLLVMRegNum(DwarfReg, true);
|
|
if (Reg == -1) {
|
|
OS << "<badreg>";
|
|
return;
|
|
}
|
|
printReg(Reg, OS, TRI);
|
|
}
|
|
|
|
void MIPrinter::print(const MCCFIInstruction &CFI,
|
|
const TargetRegisterInfo *TRI) {
|
|
switch (CFI.getOperation()) {
|
|
case MCCFIInstruction::OpSameValue:
|
|
OS << "same_value ";
|
|
if (CFI.getLabel())
|
|
OS << "<mcsymbol> ";
|
|
printCFIRegister(CFI.getRegister(), OS, TRI);
|
|
break;
|
|
case MCCFIInstruction::OpOffset:
|
|
OS << "offset ";
|
|
if (CFI.getLabel())
|
|
OS << "<mcsymbol> ";
|
|
printCFIRegister(CFI.getRegister(), OS, TRI);
|
|
OS << ", " << CFI.getOffset();
|
|
break;
|
|
case MCCFIInstruction::OpDefCfaRegister:
|
|
OS << "def_cfa_register ";
|
|
if (CFI.getLabel())
|
|
OS << "<mcsymbol> ";
|
|
printCFIRegister(CFI.getRegister(), OS, TRI);
|
|
break;
|
|
case MCCFIInstruction::OpDefCfaOffset:
|
|
OS << "def_cfa_offset ";
|
|
if (CFI.getLabel())
|
|
OS << "<mcsymbol> ";
|
|
OS << CFI.getOffset();
|
|
break;
|
|
case MCCFIInstruction::OpDefCfa:
|
|
OS << "def_cfa ";
|
|
if (CFI.getLabel())
|
|
OS << "<mcsymbol> ";
|
|
printCFIRegister(CFI.getRegister(), OS, TRI);
|
|
OS << ", " << CFI.getOffset();
|
|
break;
|
|
default:
|
|
// TODO: Print the other CFI Operations.
|
|
OS << "<unserializable cfi operation>";
|
|
break;
|
|
}
|
|
}
|
|
|
|
void llvm::printMIR(raw_ostream &OS, const Module &M) {
|
|
yaml::Output Out(OS);
|
|
Out << const_cast<Module &>(M);
|
|
}
|
|
|
|
void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
|
|
MIRPrinter Printer(OS);
|
|
Printer.print(MF);
|
|
}
|