Guozhi Wei 9def2dd316 [PPC] Prefer direct move on power8 if load 1 or 2 bytes to VSR ... Power8 has MTVSRWZ but no LXSIBZX/LXSIHZX, so move 1 or 2 bytes to VSR through MTVSRWZ is much faster than store the extended value into stack and load it with LXSIWZX. This patch fixes pr31144. Differential Revision: https://reviews.llvm.org/D27287 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289473 91177308-0d34-0410-b5e6-96231b3b80d8		2016-12-12 22:09:02 +00:00
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AArch64	instr-combiner: sum up all latencies of the transformed instructions	2016-12-11 19:39:32 +00:00
AMDGPU	[Verifier] Add verification for TBAA metadata	2016-12-11 20:07:15 +00:00
ARM	[Verifier] Add verification for TBAA metadata	2016-12-11 20:07:15 +00:00
AVR	[AVR] Add calling convention CodeGen tests	2016-12-11 07:09:45 +00:00
BPF
Generic
Hexagon
Inputs
Lanai
Mips
MIR	AMDGPU: Fix handling of 16-bit immediates	2016-12-10 00:39:12 +00:00
MSP430
NVPTX
PowerPC	[PPC] Prefer direct move on power8 if load 1 or 2 bytes to VSR	2016-12-12 22:09:02 +00:00
SPARC
SystemZ
Thumb
Thumb2
WebAssembly
WinEH
X86	Recommit r288212: Emit 'no line' information for interesting 'orphan' instructions.	2016-12-12 20:49:11 +00:00
XCore