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02cd01c121
Summary: The goal is for each operand type to have its own parse function and at the same time share common code for tracking state as different instruction types share operand types (e.g. glc/glc_flat, etc). Introduce parseAMDGPUOperand which can parse any optional operand. DPP and Clamp/OMod have custom handling for now. Sam also suggested to have class hierarchy for operand types instead of table. This can be done in separate change. Remove parseVOP3OptionalOps, parseDS*OptionalOps, parseFlatOptionalOps, parseMubufOptionalOps, parseDPPOptionalOps. Reduce number of definitions of AsmOperand's and MatchClasses' by using common base class. Rename AsmMatcher/InstPrinter methods accordingly. Print immediate type when printing parsed immediate operand. Use 'off' if offset/index register is unused instead of skipping it to make it more readable (also agreed with SP3). Update tests. Reviewers: tstellarAMD, SamWot, artem.tamazov Subscribers: qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19584 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268015 91177308-0d34-0410-b5e6-96231b3b80d8
252 lines
12 KiB
LLVM
252 lines
12 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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declare i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* nocapture, i32) #2
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declare i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* nocapture, i32) #2
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declare i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* nocapture, i64) #2
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declare i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* nocapture, i64) #2
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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; GCN-LABEL: {{^}}lds_atomic_inc_ret_i32:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]
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define void @lds_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) #0 {
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%result = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %ptr, i32 42)
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}lds_atomic_inc_ret_i32_offset:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]] offset:16
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define void @lds_atomic_inc_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) #0 {
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%gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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%result = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %gep, i32 42)
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i32:
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; GCN: s_load_dword [[SPTR:s[0-9]+]],
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; GCN: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
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; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
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; GCN: ds_inc_u32 [[VPTR]], [[DATA]]
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define void @lds_atomic_inc_noret_i32(i32 addrspace(3)* %ptr) nounwind {
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%result = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %ptr, i32 42)
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ret void
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}
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; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i32_offset:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; GCN: ds_inc_u32 v{{[0-9]+}}, [[K]] offset:16
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define void @lds_atomic_inc_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
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%gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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%result = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %gep, i32 42)
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_inc_ret_i32:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; GCN: buffer_atomic_inc [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 glc{{$}}
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define void @global_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
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%result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %ptr, i32 42)
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_inc_ret_i32_offset:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; GCN: buffer_atomic_inc [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16 glc{{$}}
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define void @global_atomic_inc_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
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%gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
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%result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42)
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}global_atomic_inc_noret_i32:
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; GCN: buffer_atomic_inc [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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define void @global_atomic_inc_noret_i32(i32 addrspace(1)* %ptr) nounwind {
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%result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %ptr, i32 42)
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ret void
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}
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; FUNC-LABEL: {{^}}global_atomic_inc_noret_i32_offset:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; GCN: buffer_atomic_inc [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16{{$}}
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define void @global_atomic_inc_noret_i32_offset(i32 addrspace(1)* %ptr) nounwind {
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%gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
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%result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42)
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_inc_ret_i32_offset_addr64:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; CI: buffer_atomic_inc [[K]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:20 glc{{$}}
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; VI: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
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define void @global_atomic_inc_ret_i32_offset_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.tid = getelementptr i32, i32 addrspace(1)* %ptr, i32 %id
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id
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%gep = getelementptr i32, i32 addrspace(1)* %gep.tid, i32 5
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%result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42)
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store i32 %result, i32 addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_inc_noret_i32_offset_addr64:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; CI: buffer_atomic_inc [[K]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:20{{$}}
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; VI: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
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define void @global_atomic_inc_noret_i32_offset_addr64(i32 addrspace(1)* %ptr) #0 {
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.tid = getelementptr i32, i32 addrspace(1)* %ptr, i32 %id
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%gep = getelementptr i32, i32 addrspace(1)* %gep.tid, i32 5
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%result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42)
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ret void
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}
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@lds0 = addrspace(3) global [512 x i32] undef, align 4
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; GCN-LABEL: {{^}}atomic_inc_shl_base_lds_0_i32:
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; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
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; GCN: ds_inc_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
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define void @atomic_inc_shl_base_lds_0_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
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%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
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%idx.0 = add nsw i32 %tid.x, 2
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%arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds0, i32 0, i32 %idx.0
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%val0 = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %arrayidx0, i32 9)
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store i32 %idx.0, i32 addrspace(1)* %add_use
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store i32 %val0, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}lds_atomic_inc_ret_i64:
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; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
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; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
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; GCN: ds_inc_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}}
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define void @lds_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 {
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%result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %ptr, i64 42)
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}lds_atomic_inc_ret_i64_offset:
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; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
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; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
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; GCN: ds_inc_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32
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define void @lds_atomic_inc_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 {
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%gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
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%result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %gep, i64 42)
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i64:
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; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
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; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
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; GCN: ds_inc_u64 v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}}
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define void @lds_atomic_inc_noret_i64(i64 addrspace(3)* %ptr) nounwind {
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%result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %ptr, i64 42)
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ret void
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}
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; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i64_offset:
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; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
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; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
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; GCN: ds_inc_u64 v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32{{$}}
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define void @lds_atomic_inc_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
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%gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
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%result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %gep, i64 42)
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_inc_ret_i64:
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; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
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; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
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; GCN: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 glc{{$}}
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define void @global_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
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%result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %ptr, i64 42)
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_inc_ret_i64_offset:
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; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
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; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
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; GCN: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:32 glc{{$}}
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define void @global_atomic_inc_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
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%gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4
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%result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42)
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}global_atomic_inc_noret_i64:
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; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
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; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
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; GCN: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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define void @global_atomic_inc_noret_i64(i64 addrspace(1)* %ptr) nounwind {
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%result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %ptr, i64 42)
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ret void
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}
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; FUNC-LABEL: {{^}}global_atomic_inc_noret_i64_offset:
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; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
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; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
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; GCN: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:32{{$}}
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define void @global_atomic_inc_noret_i64_offset(i64 addrspace(1)* %ptr) nounwind {
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%gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4
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%result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42)
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_inc_ret_i64_offset_addr64:
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; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
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; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
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; CI: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:40 glc{{$}}
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; VI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
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define void @global_atomic_inc_ret_i64_offset_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id
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%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id
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%gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5
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%result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42)
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store i64 %result, i64 addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_inc_noret_i64_offset_addr64:
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; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
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; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
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; CI: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:40{{$}}
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; VI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}}
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define void @global_atomic_inc_noret_i64_offset_addr64(i64 addrspace(1)* %ptr) #0 {
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id
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%gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5
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%result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42)
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ret void
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}
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@lds1 = addrspace(3) global [512 x i64] undef, align 8
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; GCN-LABEL: {{^}}atomic_inc_shl_base_lds_0_i64:
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; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 3, {{v[0-9]+}}
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; GCN: ds_inc_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, [[PTR]], v{{\[[0-9]+:[0-9]+\]}} offset:16
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define void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
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%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
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%idx.0 = add nsw i32 %tid.x, 2
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%arrayidx0 = getelementptr inbounds [512 x i64], [512 x i64] addrspace(3)* @lds1, i32 0, i32 %idx.0
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%val0 = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %arrayidx0, i64 9)
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store i32 %idx.0, i32 addrspace(1)* %add_use
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store i64 %val0, i64 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind argmemonly }
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