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06ed4a14fd
Summary: 1. Instruction V_CVT_U32_F32 allow omod operand (see SIInstrInfo.td:1435). In fact this operand shouldn't be allowed here. This fix checks if SDWA pseudo instruction has OMod operand and then copy it. 2. There were several problems with support of VOPC instructions in SDWA peephole pass. Reviewers: tstellar, arsenm, vpykhtin, airlied, kzhuravl Subscribers: wdng, nhaehnle, yaxunl, dstuttard, tpr, sarnex, t-tye Differential Revision: https://reviews.llvm.org/D34626 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306413 91177308-0d34-0410-b5e6-96231b3b80d8
720 lines
20 KiB
TableGen
720 lines
20 KiB
TableGen
//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===------------------------------------------------------------===//
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// Subtarget Features (device properties)
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//===------------------------------------------------------------===//
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def FeatureFP64 : SubtargetFeature<"fp64",
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"FP64",
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"true",
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"Enable double precision operations"
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>;
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def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
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"FastFMAF32",
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"true",
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"Assuming f32 fma is at least as fast as mul + add"
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>;
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def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
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"HalfRate64Ops",
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"true",
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"Most fp64 instructions are half rate instead of quarter"
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>;
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def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
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"R600ALUInst",
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"false",
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"Older version of ALU instructions encoding"
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>;
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def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
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"HasVertexCache",
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"true",
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"Specify use of dedicated vertex cache"
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>;
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def FeatureCaymanISA : SubtargetFeature<"caymanISA",
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"CaymanISA",
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"true",
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"Use Cayman ISA"
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>;
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def FeatureCFALUBug : SubtargetFeature<"cfalubug",
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"CFALUBug",
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"true",
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"GPU has CF_ALU bug"
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>;
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def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
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"FlatAddressSpace",
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"true",
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"Support flat address space"
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>;
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def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
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"FlatInstOffsets",
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"true",
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"Flat instructions have immediate offset addressing mode"
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>;
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def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
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"FlatGlobalInsts",
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"true",
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"Have global_* flat memory instructions"
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>;
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def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
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"FlatScratchInsts",
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"true",
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"Have scratch_* flat memory instructions"
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>;
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def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
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"UnalignedBufferAccess",
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"true",
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"Support unaligned global loads and stores"
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>;
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def FeatureTrapHandler: SubtargetFeature<"trap-handler",
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"TrapHandler",
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"true",
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"Trap handler support"
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>;
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def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
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"UnalignedScratchAccess",
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"true",
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"Support unaligned scratch loads and stores"
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>;
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def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
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"HasApertureRegs",
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"true",
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"Has Memory Aperture Base and Size Registers"
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>;
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// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
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// XNACK. The current default kernel driver setting is:
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// - graphics ring: XNACK disabled
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// - compute ring: XNACK enabled
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//
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// If XNACK is enabled, the VMEM latency can be worse.
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// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
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def FeatureXNACK : SubtargetFeature<"xnack",
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"EnableXNACK",
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"true",
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"Enable XNACK support"
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>;
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def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
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"SGPRInitBug",
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"true",
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"VI SGPR initilization bug requiring a fixed SGPR allocation size"
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>;
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class SubtargetFeatureFetchLimit <string Value> :
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SubtargetFeature <"fetch"#Value,
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"TexVTXClauseSize",
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Value,
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"Limit the maximum number of fetches in a clause to "#Value
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>;
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def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
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def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
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class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
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"wavefrontsize"#Value,
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"WavefrontSize",
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!cast<string>(Value),
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"The number of threads per wavefront"
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>;
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def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
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def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
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def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
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class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
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"ldsbankcount"#Value,
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"LDSBankCount",
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!cast<string>(Value),
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"The number of LDS banks per compute unit."
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>;
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def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
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def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
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class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
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"localmemorysize"#Value,
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"LocalMemorySize",
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!cast<string>(Value),
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"The size of local memory in bytes"
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>;
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def FeatureGCN : SubtargetFeature<"gcn",
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"IsGCN",
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"true",
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"GCN or newer GPU"
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>;
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def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
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"GCN1Encoding",
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"true",
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"Encoding format for SI and CI"
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>;
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def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
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"GCN3Encoding",
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"true",
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"Encoding format for VI"
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>;
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def FeatureCIInsts : SubtargetFeature<"ci-insts",
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"CIInsts",
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"true",
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"Additional intstructions for CI+"
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>;
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def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
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"GFX9Insts",
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"true",
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"Additional intstructions for GFX9+"
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>;
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def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
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"HasSMemRealTime",
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"true",
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"Has s_memrealtime instruction"
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>;
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def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
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"HasInv2PiInlineImm",
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"true",
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"Has 1 / (2 * pi) as inline immediate"
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>;
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def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
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"Has16BitInsts",
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"true",
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"Has i16/f16 instructions"
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>;
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def FeatureVOP3P : SubtargetFeature<"vop3p",
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"HasVOP3PInsts",
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"true",
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"Has VOP3P packed instructions"
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>;
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def FeatureMovrel : SubtargetFeature<"movrel",
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"HasMovrel",
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"true",
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"Has v_movrel*_b32 instructions"
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>;
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def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
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"HasVGPRIndexMode",
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"true",
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"Has VGPR mode register indexing"
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>;
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def FeatureScalarStores : SubtargetFeature<"scalar-stores",
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"HasScalarStores",
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"true",
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"Has store scalar memory instructions"
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>;
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def FeatureSDWA : SubtargetFeature<"sdwa",
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"HasSDWA",
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"true",
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"Support SDWA (Sub-DWORD Addressing) extension"
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>;
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def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
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"HasSDWAOmod",
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"true",
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"Support OMod with SDWA (Sub-DWORD Addressing) extension"
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>;
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def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
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"HasSDWAScalar",
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"true",
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"Support scalar register with SDWA (Sub-DWORD Addressing) extension"
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>;
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def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
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"HasSDWASdst",
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"true",
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"Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
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>;
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def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
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"HasSDWAMac",
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"true",
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"Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
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>;
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def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
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"HasSDWAOutModsVOPC",
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"true",
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"Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
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>;
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def FeatureDPP : SubtargetFeature<"dpp",
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"HasDPP",
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"true",
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"Support DPP (Data Parallel Primitives) extension"
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>;
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//===------------------------------------------------------------===//
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// Subtarget Features (options and debugging)
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//===------------------------------------------------------------===//
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// Some instructions do not support denormals despite this flag. Using
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// fp32 denormals also causes instructions to run at the double
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// precision rate for the device.
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def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
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"FP32Denormals",
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"true",
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"Enable single precision denormal handling"
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>;
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// Denormal handling for fp64 and fp16 is controlled by the same
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// config register when fp16 supported.
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// TODO: Do we need a separate f16 setting when not legal?
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def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
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"FP64FP16Denormals",
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"true",
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"Enable double and half precision denormal handling",
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[FeatureFP64]
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>;
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def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
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"FP64FP16Denormals",
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"true",
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"Enable double and half precision denormal handling",
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[FeatureFP64, FeatureFP64FP16Denormals]
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>;
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def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
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"FP64FP16Denormals",
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"true",
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"Enable half precision denormal handling",
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[FeatureFP64FP16Denormals]
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>;
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def FeatureDX10Clamp : SubtargetFeature<"dx10-clamp",
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"DX10Clamp",
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"true",
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"clamp modifier clamps NaNs to 0.0"
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>;
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def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
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"FPExceptions",
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"true",
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"Enable floating point exceptions"
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>;
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class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
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"max-private-element-size-"#size,
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"MaxPrivateElementSize",
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!cast<string>(size),
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"Maximum private access size may be "#size
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>;
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def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
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def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
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def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
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def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
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"EnableVGPRSpilling",
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"true",
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"Enable spilling of VGPRs to scratch memory"
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>;
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def FeatureDumpCode : SubtargetFeature <"DumpCode",
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"DumpCode",
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"true",
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"Dump MachineInstrs in the CodeEmitter"
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>;
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def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
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"DumpCode",
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"true",
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"Dump MachineInstrs in the CodeEmitter"
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>;
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def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
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"EnablePromoteAlloca",
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"true",
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"Enable promote alloca pass"
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>;
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// XXX - This should probably be removed once enabled by default
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def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
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"EnableLoadStoreOpt",
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"true",
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"Enable SI load/store optimizer pass"
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>;
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// Performance debugging feature. Allow using DS instruction immediate
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// offsets even if the base pointer can't be proven to be base. On SI,
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// base pointer values that won't give the same result as a 16-bit add
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// are not safe to fold, but this will override the conservative test
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// for the base pointer.
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def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
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"unsafe-ds-offset-folding",
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"EnableUnsafeDSOffsetFolding",
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"true",
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"Force using DS instruction immediate offsets on SI"
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>;
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def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
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"EnableSIScheduler",
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"true",
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"Enable SI Machine Scheduler"
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>;
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// Unless +-flat-for-global is specified, turn on FlatForGlobal for
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// all OS-es on VI and newer hardware to avoid assertion failures due
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// to missing ADDR64 variants of MUBUF instructions.
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// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
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// instructions.
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def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
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"FlatForGlobal",
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"true",
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"Force to generate flat instruction for global"
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>;
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def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
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"auto-waitcnt-before-barrier",
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"AutoWaitcntBeforeBarrier",
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"true",
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"Hardware automatically inserts waitcnt before barrier"
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>;
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// Dummy feature used to disable assembler instructions.
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def FeatureDisable : SubtargetFeature<"",
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"FeatureDisable","true",
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"Dummy feature to disable assembler instructions"
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>;
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class SubtargetFeatureGeneration <string Value,
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list<SubtargetFeature> Implies> :
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SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
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Value#" GPU generation", Implies>;
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def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
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def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
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def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
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def FeatureR600 : SubtargetFeatureGeneration<"R600",
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[FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]
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>;
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def FeatureR700 : SubtargetFeatureGeneration<"R700",
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[FeatureFetchLimit16, FeatureLocalMemorySize0]
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>;
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def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
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[FeatureFetchLimit16, FeatureLocalMemorySize32768]
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>;
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def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
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[FeatureFetchLimit16, FeatureWavefrontSize64,
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FeatureLocalMemorySize32768]
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>;
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def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
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[FeatureFP64, FeatureLocalMemorySize32768,
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FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
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FeatureLDSBankCount32, FeatureMovrel]
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>;
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def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
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[FeatureFP64, FeatureLocalMemorySize65536,
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FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
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FeatureGCN1Encoding, FeatureCIInsts, FeatureMovrel]
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>;
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def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
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[FeatureFP64, FeatureLocalMemorySize65536,
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FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
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FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
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FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
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FeatureScalarStores, FeatureInv2PiInlineImm,
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FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP
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]
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>;
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def FeatureGFX9 : SubtargetFeatureGeneration<"GFX9",
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[FeatureFP64, FeatureLocalMemorySize65536,
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FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
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FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
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FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
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FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
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FeatureFastFMAF32, FeatureDPP,
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FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
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FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts
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]
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>;
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class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
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list<SubtargetFeature> Implies>
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: SubtargetFeature <
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"isaver"#Major#"."#Minor#"."#Stepping,
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"IsaVersion",
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"ISAVersion"#Major#"_"#Minor#"_"#Stepping,
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"Instruction set version number",
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Implies
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>;
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def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
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[FeatureSouthernIslands,
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FeatureFastFMAF32,
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HalfRate64Ops,
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FeatureLDSBankCount32]>;
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def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
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[FeatureSouthernIslands,
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FeatureLDSBankCount32]>;
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def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
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[FeatureSeaIslands,
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FeatureLDSBankCount32]>;
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def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
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[FeatureSeaIslands,
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HalfRate64Ops,
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FeatureLDSBankCount32,
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FeatureFastFMAF32]>;
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def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
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[FeatureSeaIslands,
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FeatureLDSBankCount16]>;
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def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
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[FeatureSeaIslands,
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FeatureLDSBankCount16]>;
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def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0,
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[FeatureVolcanicIslands,
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FeatureLDSBankCount32,
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FeatureSGPRInitBug]>;
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def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
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[FeatureVolcanicIslands,
|
|
FeatureLDSBankCount32,
|
|
FeatureXNACK]>;
|
|
|
|
def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
|
|
[FeatureVolcanicIslands,
|
|
FeatureLDSBankCount32,
|
|
FeatureSGPRInitBug]>;
|
|
|
|
def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
|
|
[FeatureVolcanicIslands,
|
|
FeatureLDSBankCount32]>;
|
|
|
|
def FeatureISAVersion8_0_4 : SubtargetFeatureISAVersion <8,0,4,
|
|
[FeatureVolcanicIslands,
|
|
FeatureLDSBankCount32]>;
|
|
|
|
def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
|
|
[FeatureVolcanicIslands,
|
|
FeatureLDSBankCount16,
|
|
FeatureXNACK]>;
|
|
|
|
def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
|
|
[FeatureGFX9,
|
|
FeatureLDSBankCount32]>;
|
|
|
|
def FeatureISAVersion9_0_1 : SubtargetFeatureISAVersion <9,0,1,
|
|
[FeatureGFX9,
|
|
FeatureLDSBankCount32,
|
|
FeatureXNACK]>;
|
|
|
|
def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
|
|
[FeatureGFX9,
|
|
FeatureLDSBankCount32]>;
|
|
|
|
def FeatureISAVersion9_0_3 : SubtargetFeatureISAVersion <9,0,3,
|
|
[FeatureGFX9,
|
|
FeatureLDSBankCount32,
|
|
FeatureXNACK]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Debugger related subtarget features.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def FeatureDebuggerInsertNops : SubtargetFeature<
|
|
"amdgpu-debugger-insert-nops",
|
|
"DebuggerInsertNops",
|
|
"true",
|
|
"Insert one nop instruction for each high level source statement"
|
|
>;
|
|
|
|
def FeatureDebuggerReserveRegs : SubtargetFeature<
|
|
"amdgpu-debugger-reserve-regs",
|
|
"DebuggerReserveRegs",
|
|
"true",
|
|
"Reserve registers for debugger usage"
|
|
>;
|
|
|
|
def FeatureDebuggerEmitPrologue : SubtargetFeature<
|
|
"amdgpu-debugger-emit-prologue",
|
|
"DebuggerEmitPrologue",
|
|
"true",
|
|
"Emit debugger prologue"
|
|
>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def AMDGPUInstrInfo : InstrInfo {
|
|
let guessInstructionProperties = 1;
|
|
let noNamedPositionallyEncodedOperands = 1;
|
|
}
|
|
|
|
def AMDGPUAsmParser : AsmParser {
|
|
// Some of the R600 registers have the same name, so this crashes.
|
|
// For example T0_XYZW and T0_XY both have the asm name T0.
|
|
let ShouldEmitMatchRegisterName = 0;
|
|
}
|
|
|
|
def AMDGPUAsmWriter : AsmWriter {
|
|
int PassSubtarget = 1;
|
|
}
|
|
|
|
def AMDGPUAsmVariants {
|
|
string Default = "Default";
|
|
int Default_ID = 0;
|
|
string VOP3 = "VOP3";
|
|
int VOP3_ID = 1;
|
|
string SDWA = "SDWA";
|
|
int SDWA_ID = 2;
|
|
string SDWA9 = "SDWA9";
|
|
int SDWA9_ID = 3;
|
|
string DPP = "DPP";
|
|
int DPP_ID = 4;
|
|
string Disable = "Disable";
|
|
int Disable_ID = 5;
|
|
}
|
|
|
|
def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
|
|
let Variant = AMDGPUAsmVariants.Default_ID;
|
|
let Name = AMDGPUAsmVariants.Default;
|
|
}
|
|
|
|
def VOP3AsmParserVariant : AsmParserVariant {
|
|
let Variant = AMDGPUAsmVariants.VOP3_ID;
|
|
let Name = AMDGPUAsmVariants.VOP3;
|
|
}
|
|
|
|
def SDWAAsmParserVariant : AsmParserVariant {
|
|
let Variant = AMDGPUAsmVariants.SDWA_ID;
|
|
let Name = AMDGPUAsmVariants.SDWA;
|
|
}
|
|
|
|
def SDWA9AsmParserVariant : AsmParserVariant {
|
|
let Variant = AMDGPUAsmVariants.SDWA9_ID;
|
|
let Name = AMDGPUAsmVariants.SDWA9;
|
|
}
|
|
|
|
|
|
def DPPAsmParserVariant : AsmParserVariant {
|
|
let Variant = AMDGPUAsmVariants.DPP_ID;
|
|
let Name = AMDGPUAsmVariants.DPP;
|
|
}
|
|
|
|
def AMDGPU : Target {
|
|
// Pull in Instruction Info:
|
|
let InstructionSet = AMDGPUInstrInfo;
|
|
let AssemblyParsers = [AMDGPUAsmParser];
|
|
let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
|
|
VOP3AsmParserVariant,
|
|
SDWAAsmParserVariant,
|
|
SDWA9AsmParserVariant,
|
|
DPPAsmParserVariant];
|
|
let AssemblyWriters = [AMDGPUAsmWriter];
|
|
}
|
|
|
|
// Dummy Instruction itineraries for pseudo instructions
|
|
def ALU_NULL : FuncUnit;
|
|
def NullALU : InstrItinClass;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Predicate helper class
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def TruePredicate : Predicate<"true">;
|
|
|
|
def isSICI : Predicate<
|
|
"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
|
|
"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
|
|
>, AssemblerPredicate<"FeatureGCN1Encoding">;
|
|
|
|
def isVI : Predicate <
|
|
"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
|
|
AssemblerPredicate<"FeatureGCN3Encoding">;
|
|
|
|
def isGFX9 : Predicate <
|
|
"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
|
|
AssemblerPredicate<"FeatureGFX9Insts">;
|
|
|
|
// TODO: Either the name to be changed or we simply use IsCI!
|
|
def isCIVI : Predicate <
|
|
"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
|
|
AssemblerPredicate<"FeatureCIInsts">;
|
|
|
|
def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
|
|
AssemblerPredicate<"FeatureFlatAddressSpace">;
|
|
|
|
def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
|
|
AssemblerPredicate<"FeatureFlatGlobalInsts">;
|
|
|
|
def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
|
|
AssemblerPredicate<"Feature16BitInsts">;
|
|
def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
|
|
AssemblerPredicate<"FeatureVOP3P">;
|
|
|
|
def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
|
|
AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
|
|
|
|
def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
|
|
AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
|
|
|
|
def HasDPP : Predicate<"Subtarget->hasDPP()">,
|
|
AssemblerPredicate<"FeatureDPP">;
|
|
|
|
class PredicateControl {
|
|
Predicate SubtargetPredicate;
|
|
Predicate SIAssemblerPredicate = isSICI;
|
|
Predicate VIAssemblerPredicate = isVI;
|
|
list<Predicate> AssemblerPredicates = [];
|
|
Predicate AssemblerPredicate = TruePredicate;
|
|
list<Predicate> OtherPredicates = [];
|
|
list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
|
|
AssemblerPredicates,
|
|
OtherPredicates);
|
|
}
|
|
|
|
// Include AMDGPU TD files
|
|
include "R600Schedule.td"
|
|
include "SISchedule.td"
|
|
include "Processors.td"
|
|
include "AMDGPUInstrInfo.td"
|
|
include "AMDGPUIntrinsics.td"
|
|
include "AMDGPURegisterInfo.td"
|
|
include "AMDGPURegisterBanks.td"
|
|
include "AMDGPUInstructions.td"
|
|
include "AMDGPUCallingConv.td"
|