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43733c2252
Summary: The backend has no reason to behave like a driver and should generally do as it's told (and error out if it can't) instead of trying to figure out what the API user meant. The default ABI is still derived from the arch component as a concession to backwards compatibility. API-users that previously passed an explicit CPU and a triple that was inconsistent with the CPU (e.g. mips-linux-gnu and mips64r2) may get a different ABI to what they got before. However, it's expected that there are no such users on the basis that CodeGen has been asserting that the triple is consistent with the selected ABI for several releases. API-users that were consistent or passed '' or 'generic' as the CPU will see no difference. Reviewers: sdardis, rafael Subscribers: rafael, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21466 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273557 91177308-0d34-0410-b5e6-96231b3b80d8
121 lines
3.4 KiB
C++
121 lines
3.4 KiB
C++
//===---- MipsABIInfo.cpp - Information about MIPS ABI's ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsABIInfo.h"
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#include "MipsRegisterInfo.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/MC/MCTargetOptions.h"
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using namespace llvm;
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namespace {
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static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
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static const MCPhysReg Mips64IntRegs[8] = {
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Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
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Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
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}
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ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const {
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if (IsO32())
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return makeArrayRef(O32IntRegs);
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if (IsN32() || IsN64())
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return makeArrayRef(Mips64IntRegs);
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llvm_unreachable("Unhandled ABI");
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}
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ArrayRef<MCPhysReg> MipsABIInfo::GetVarArgRegs() const {
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if (IsO32())
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return makeArrayRef(O32IntRegs);
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if (IsN32() || IsN64())
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return makeArrayRef(Mips64IntRegs);
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llvm_unreachable("Unhandled ABI");
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}
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unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const {
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if (IsO32())
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return CC != CallingConv::Fast ? 16 : 0;
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if (IsN32() || IsN64())
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return 0;
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llvm_unreachable("Unhandled ABI");
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}
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MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef CPU,
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const MCTargetOptions &Options) {
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if (Options.getABIName().startswith("o32"))
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return MipsABIInfo::O32();
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else if (Options.getABIName().startswith("n32"))
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return MipsABIInfo::N32();
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else if (Options.getABIName().startswith("n64"))
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return MipsABIInfo::N64();
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else if (!Options.getABIName().empty())
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llvm_unreachable("Unknown ABI option for MIPS");
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if (TT.getArch() == Triple::mips64 || TT.getArch() == Triple::mips64el)
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return MipsABIInfo::N64();
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return MipsABIInfo::O32();
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}
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unsigned MipsABIInfo::GetStackPtr() const {
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return ArePtrs64bit() ? Mips::SP_64 : Mips::SP;
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}
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unsigned MipsABIInfo::GetFramePtr() const {
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return ArePtrs64bit() ? Mips::FP_64 : Mips::FP;
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}
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unsigned MipsABIInfo::GetBasePtr() const {
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return ArePtrs64bit() ? Mips::S7_64 : Mips::S7;
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}
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unsigned MipsABIInfo::GetGlobalPtr() const {
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return ArePtrs64bit() ? Mips::GP_64 : Mips::GP;
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}
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unsigned MipsABIInfo::GetNullPtr() const {
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return ArePtrs64bit() ? Mips::ZERO_64 : Mips::ZERO;
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}
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unsigned MipsABIInfo::GetZeroReg() const {
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return AreGprs64bit() ? Mips::ZERO_64 : Mips::ZERO;
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}
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unsigned MipsABIInfo::GetPtrAdduOp() const {
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return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu;
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}
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unsigned MipsABIInfo::GetPtrAddiuOp() const {
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return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu;
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}
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unsigned MipsABIInfo::GetPtrSubuOp() const {
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return ArePtrs64bit() ? Mips::DSUBu : Mips::SUBu;
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}
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unsigned MipsABIInfo::GetPtrAndOp() const {
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return ArePtrs64bit() ? Mips::AND64 : Mips::AND;
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}
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unsigned MipsABIInfo::GetGPRMoveOp() const {
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return ArePtrs64bit() ? Mips::OR64 : Mips::OR;
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}
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unsigned MipsABIInfo::GetEhDataReg(unsigned I) const {
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static const unsigned EhDataReg[] = {
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Mips::A0, Mips::A1, Mips::A2, Mips::A3
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};
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static const unsigned EhDataReg64[] = {
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Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
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};
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return IsN64() ? EhDataReg64[I] : EhDataReg[I];
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}
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