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0035f9c3b9
For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public interface" it must be 8-byte aligned. For the older ARM APCS ABI, the stack alignment is just always 4 bytes. For X86, we currently align SP at entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment is needed at other times, such as for a leaf function. After discussing this with Dan, I decided to go with the approach of adding a new "TransientStackAlignment" field to TargetFrameInfo. This value specifies the stack alignment that must be maintained even in between calls. It defaults to 1 except for ARM, where it is 4. (Some other targets may also want to set this if they have similar stack requirements. It's not currently required for PPC because it sets targetHandlesStackFrameRounding and handles the alignment in target-specific code.) The existing StackAlignment value specifies the alignment upon entry to a function, which is how we've been using it anyway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82767 91177308-0d34-0410-b5e6-96231b3b80d8
18 lines
639 B
LLVM
18 lines
639 B
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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; pr4926
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define arm_apcscc void @test_vget_lanep16() nounwind {
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entry:
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%arg0_poly16x4_t = alloca <4 x i16> ; <<4 x i16>*> [#uses=1]
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%out_poly16_t = alloca i16 ; <i16*> [#uses=1]
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%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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; CHECK: fldd
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%0 = load <4 x i16>* %arg0_poly16x4_t, align 8 ; <<4 x i16>> [#uses=1]
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%1 = extractelement <4 x i16> %0, i32 1 ; <i16> [#uses=1]
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store i16 %1, i16* %out_poly16_t, align 2
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br label %return
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return: ; preds = %entry
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ret void
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}
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