llvm/CodeGen at e817bdd304e89b1e0d6fcadba1c66466625e704a - llvm

RPCSX/llvm

mirror of https://github.com/RPCSX/llvm.git synced 2025-02-23 22:52:48 +00:00

History

Quentin Colombet e817bdd304 [PeepholeOptimizer] Take advantage of the isInsertSubreg property in the

advanced copy optimization.

This is the final step patch toward transforming:
udiv    r0, r0, r2
udiv    r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov    r0, r1, d16
bx      lr

into:
udiv    r0, r0, r2
udiv    r1, r1, r3
bx      lr

Indeed, thanks to this patch, this optimization is able to look through
vmov.32 d16[0], r0
vmov.32 d16[1], r1

and is able to rewrite the following sequence:
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov    r0, r1, d16

into simple generic GPR copies that the coalescer managed to remove.

<rdar://problem/12702965>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216144 91177308-0d34-0410-b5e6-96231b3b80d8

2014-08-21 00:19:16 +00:00

AArch64

[FastISel][AArch64] Don't fold the sign-/zero-extend from i1 into the compare.

2014-08-20 16:34:15 +00:00

ARM

[PeepholeOptimizer] Take advantage of the isInsertSubreg property in the

2014-08-21 00:19:16 +00:00

CPP

…

Generic

Use "weak alias" instead of "alias weak"

2014-07-30 22:51:54 +00:00