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Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250407 91177308-0d34-0410-b5e6-96231b3b80d8
39 lines
1.4 KiB
LLVM
39 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s
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@x = global float 0.000000e+00, align 4
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@.str = private unnamed_addr constant [20 x i8] c"in main: mips16 %f\0A\00", align 1
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; Function Attrs: nounwind
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define void @foo() #0 {
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entry:
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%0 = load float, float* @x, align 4
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%conv = fpext float %0 to double
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%add = fadd double %conv, 1.500000e+00
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%conv1 = fptrunc double %add to float
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store float %conv1, float* @x, align 4
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ret void
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}
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; CHECK: .ent foo
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; CHECK: jal __mips16_extendsfdf2
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; CHECK: .end foo
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; Function Attrs: nounwind
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define void @nofoo() #1 {
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entry:
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%0 = load float, float* @x, align 4
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%conv = fpext float %0 to double
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%add = fadd double %conv, 3.900000e+00
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%conv1 = fptrunc double %add to float
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store float %conv1, float* @x, align 4
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ret void
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}
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; CHECK: .ent nofoo
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; CHECK: cvt.d.s $f{{.+}}, $f{{.+}}
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; CHECK: .end nofoo
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attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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