Tim Northover ef5f53b78f ARM64: disable printing of "lslv" type aliases ...

You can write "lslv w0, w1, w2" (probably for legacy reasons), but it should be
printed as simply "lsl".

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208956 91177308-0d34-0410-b5e6-96231b3b80d8

2014-05-16 09:40:52 +00:00

..

AsmParser

[ARM64] Improve diagnostics for Cn operands in SYS instructions

2014-05-15 16:28:32 +00:00

Disassembler

[ARM64] Parse fixed vector lanes properly so that diagnostics can be emitted

2014-05-15 11:07:57 +00:00

InstPrinter

TableGen: use correct MIOperand when printing aliases

2014-05-15 13:36:01 +00:00

MCTargetDesc

[ARM64-BE] Fix byte order of CIE and FDE frames for exception handling

2014-05-14 16:51:58 +00:00

TargetInfo

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Utils

[ARM64] Conditionalize CPU specific system registers on subtarget features

2014-05-01 10:25:36 +00:00

ARM64.h

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ARM64.td

Fix typo.

2014-05-05 21:50:57 +00:00

ARM64AddressTypePromotion.cpp

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ARM64AdvSIMDScalarPass.cpp

[ARM64][fast-isel] Disable target specific optimizations at -O0. Functionally,

2014-05-07 16:41:55 +00:00

ARM64AsmPrinter.cpp

AArch64/ARM64: support indexed loads/stores on vector types.

2014-05-02 14:54:15 +00:00

ARM64BranchRelaxation.cpp

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ARM64CallingConv.h

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ARM64CallingConvention.td

[ARM64-BE] Implement the lane-twiddling logic at AAPCS boundaries for big endian.

2014-05-07 12:33:41 +00:00

ARM64CleanupLocalDynamicTLSPass.cpp

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ARM64CollectLOH.cpp

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ARM64ConditionalCompares.cpp

AArch64/ARM64: expunge CPSR from the sources

2014-04-30 13:14:14 +00:00

ARM64DeadRegisterDefinitionsPass.cpp

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ARM64ExpandPseudoInsts.cpp

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ARM64FastISel.cpp

[ARM64-BE] Teach fast-isel about how to set up sub-word stack arguments for big endian calls.

2014-05-08 12:53:50 +00:00

ARM64FrameLowering.cpp

[ARM64] Support aggressive fastcc/tailcallopt breaking ABI by popping out argument stack from callee.

2014-05-15 01:33:17 +00:00

ARM64FrameLowering.h

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ARM64InstrAtomics.td

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ARM64InstrFormats.td

ARM64: disable printing of "lslv" type aliases

2014-05-16 09:40:52 +00:00

ARM64InstrInfo.cpp

ARM64: merge "extend" and "shift" addressing-mode enums.

2014-05-12 14:13:17 +00:00

ARM64InstrInfo.h

AArch64/ARM64: expunge CPSR from the sources

2014-04-30 13:14:14 +00:00

ARM64InstrInfo.td

ARM64: print correct aliases for NEON mov & mvn instructions

2014-05-15 12:11:02 +00:00

ARM64ISelDAGToDAG.cpp

[ARM64]Implement NEON post-increment LD1(lane) and post-increment LD1R.

2014-05-16 09:39:02 +00:00

ARM64ISelLowering.cpp

[ARM64]Implement NEON post-increment LD1(lane) and post-increment LD1R.

2014-05-16 09:39:02 +00:00

ARM64ISelLowering.h

[ARM64]Implement NEON post-increment LD1(lane) and post-increment LD1R.

2014-05-16 09:39:02 +00:00

ARM64LoadStoreOptimizer.cpp

[ARM64][fast-isel] Disable target specific optimizations at -O0. Functionally,

2014-05-07 16:41:55 +00:00

ARM64MachineFunctionInfo.h

[ARM64] Support aggressive fastcc/tailcallopt breaking ABI by popping out argument stack from callee.

2014-05-15 01:33:17 +00:00

ARM64MCInstLower.cpp

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ARM64MCInstLower.h

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ARM64PerfectShuffle.h

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ARM64PromoteConstant.cpp

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ARM64RegisterInfo.cpp

AArch64/ARM64: expunge CPSR from the sources

2014-04-30 13:14:14 +00:00

ARM64RegisterInfo.h

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ARM64RegisterInfo.td

ARM64: add correct vector registers during asm parsing

2014-05-15 11:16:19 +00:00

ARM64SchedA53.td

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ARM64SchedCyclone.td

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ARM64Schedule.td

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ARM64SelectionDAGInfo.cpp

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ARM64SelectionDAGInfo.h

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ARM64StorePairSuppress.cpp

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ARM64Subtarget.cpp

[ARM64] Prefer generation of bzero on Darwin only

2014-05-01 13:11:59 +00:00

ARM64Subtarget.h

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ARM64TargetMachine.cpp

[ARM64][fast-isel] Disable target specific optimizations at -O0. Functionally,

2014-05-07 16:41:55 +00:00

ARM64TargetMachine.h

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ARM64TargetObjectFile.cpp

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ARM64TargetObjectFile.h

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ARM64TargetTransformInfo.cpp

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CMakeLists.txt

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LLVMBuild.txt

Fix broken build

2014-05-09 18:06:22 +00:00

Makefile

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