llvm/test/MC/Disassembler
Artem Tamazov 3398735496 [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed.
Fixes Bug 28215. Lit tests updated.

Differential Revision: https://reviews.llvm.org/D25837

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284825 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-21 14:49:22 +00:00
..
AArch64 AArch64: TableGenerate system instruction operands. 2016-07-05 21:23:04 +00:00
AMDGPU [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed. 2016-10-21 14:49:22 +00:00
ARM [ARM] Saturation instructions are DSP-only 2016-07-25 22:25:25 +00:00
Hexagon [Hexagon] Treat all conditional branches as predicted (not-taken by default) 2016-05-09 18:22:07 +00:00
Lanai [lanai] Add Lanai backend. 2016-03-28 13:09:54 +00:00
Mips [mips] Fix aui/daui/dahi/dati for MIPSR6 2016-10-14 09:31:42 +00:00
PowerPC [PowerPC] Add asm parser/disassembler support for hrfid,nap,slbmfev 2016-09-02 23:42:01 +00:00
Sparc This change adds co-processor condition branching and conditional traps to the Sparc back-end. 2016-03-09 18:20:21 +00:00
SystemZ [SystemZ] Add missing vector instructions for the assembler 2016-10-19 13:03:18 +00:00
X86 Add new flag and intrinsic support for MWAITX and MONITORX instructions 2016-05-18 11:59:12 +00:00
XCore Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00