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The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
32 lines
966 B
LLVM
32 lines
966 B
LLVM
; RUN: llc < %s -march=x86-64 | grep movd | count 4
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define i64 @foo(x86_mmx* %p) {
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%t = load x86_mmx* %p
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%u = tail call x86_mmx @llvm.x86.mmx.padd.q(x86_mmx %t, x86_mmx %t)
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%s = bitcast x86_mmx %u to i64
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ret i64 %s
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}
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define i64 @goo(x86_mmx* %p) {
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%t = load x86_mmx* %p
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%u = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %t, x86_mmx %t)
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%s = bitcast x86_mmx %u to i64
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ret i64 %s
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}
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define i64 @hoo(x86_mmx* %p) {
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%t = load x86_mmx* %p
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%u = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %t, x86_mmx %t)
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%s = bitcast x86_mmx %u to i64
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ret i64 %s
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}
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define i64 @ioo(x86_mmx* %p) {
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%t = load x86_mmx* %p
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%u = tail call x86_mmx @llvm.x86.mmx.padd.b(x86_mmx %t, x86_mmx %t)
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%s = bitcast x86_mmx %u to i64
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ret i64 %s
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}
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declare x86_mmx @llvm.x86.mmx.padd.b(x86_mmx, x86_mmx)
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declare x86_mmx @llvm.x86.mmx.padd.w(x86_mmx, x86_mmx)
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declare x86_mmx @llvm.x86.mmx.padd.d(x86_mmx, x86_mmx)
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declare x86_mmx @llvm.x86.mmx.padd.q(x86_mmx, x86_mmx)
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