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This patch corresponds to review: http://reviews.llvm.org/D20239 It adds exploitation of XXINSERTW and XXEXTRACTUW instructions that are useful in some cases for inserting and extracting vector elements of v4[if]32 vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275215 91177308-0d34-0410-b5e6-96231b3b80d8
606 lines
22 KiB
Plaintext
606 lines
22 KiB
Plaintext
//===- README_P9.txt - Notes for improving Power9 code gen ----------------===//
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TODO: Instructions Need Implement Instrinstics or Map to LLVM IR
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Altivec:
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- Vector Compare Not Equal (Zero):
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vcmpneb(.) vcmpneh(.) vcmpnew(.)
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vcmpnezb(.) vcmpnezh(.) vcmpnezw(.)
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. Same as other VCMP*, use VCMP/VCMPo form (support intrinsic)
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- Vector Extract Unsigned: vextractub vextractuh vextractuw vextractd
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. Don't use llvm extractelement because they have different semantics
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. Use instrinstics:
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(set v2i64:$vD, (int_ppc_altivec_vextractub v16i8:$vA, imm:$UIMM))
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(set v2i64:$vD, (int_ppc_altivec_vextractuh v8i16:$vA, imm:$UIMM))
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(set v2i64:$vD, (int_ppc_altivec_vextractuw v4i32:$vA, imm:$UIMM))
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(set v2i64:$vD, (int_ppc_altivec_vextractd v2i64:$vA, imm:$UIMM))
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- Vector Extract Unsigned Byte Left/Right-Indexed:
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vextublx vextubrx vextuhlx vextuhrx vextuwlx vextuwrx
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. Use instrinstics:
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// Left-Indexed
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(set i64:$rD, (int_ppc_altivec_vextublx i64:$rA, v16i8:$vB))
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(set i64:$rD, (int_ppc_altivec_vextuhlx i64:$rA, v8i16:$vB))
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(set i64:$rD, (int_ppc_altivec_vextuwlx i64:$rA, v4i32:$vB))
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// Right-Indexed
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(set i64:$rD, (int_ppc_altivec_vextubrx i64:$rA, v16i8:$vB))
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(set i64:$rD, (int_ppc_altivec_vextuhrx i64:$rA, v8i16:$vB))
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(set i64:$rD, (int_ppc_altivec_vextuwrx i64:$rA, v4i32:$vB))
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- Vector Insert Element Instructions: vinsertb vinsertd vinserth vinsertw
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(set v16i8:$vD, (int_ppc_altivec_vinsertb v16i8:$vA, imm:$UIMM))
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(set v8i16:$vD, (int_ppc_altivec_vinsertd v8i16:$vA, imm:$UIMM))
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(set v4i32:$vD, (int_ppc_altivec_vinserth v4i32:$vA, imm:$UIMM))
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(set v2i64:$vD, (int_ppc_altivec_vinsertw v2i64:$vA, imm:$UIMM))
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- Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD]:
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vclzlsbb vctzlsbb
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. Use intrinsic:
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(set i64:$rD, (int_ppc_altivec_vclzlsbb v16i8:$vB))
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(set i64:$rD, (int_ppc_altivec_vctzlsbb v16i8:$vB))
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- Vector Count Trailing Zeros: vctzb vctzh vctzw vctzd
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. Map to llvm cttz
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(set v16i8:$vD, (cttz v16i8:$vB)) // vctzb
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(set v8i16:$vD, (cttz v8i16:$vB)) // vctzh
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(set v4i32:$vD, (cttz v4i32:$vB)) // vctzw
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(set v2i64:$vD, (cttz v2i64:$vB)) // vctzd
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- Vector Extend Sign: vextsb2w vextsh2w vextsb2d vextsh2d vextsw2d
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. vextsb2w:
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(set v4i32:$vD, (sext v4i8:$vB))
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// PowerISA_V3.0:
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do i = 0 to 3
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VR[VRT].word[i] ← EXTS32(VR[VRB].word[i].byte[3])
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end
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. vextsh2w:
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(set v4i32:$vD, (sext v4i16:$vB))
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// PowerISA_V3.0:
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do i = 0 to 3
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VR[VRT].word[i] ← EXTS32(VR[VRB].word[i].hword[1])
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end
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. vextsb2d
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(set v2i64:$vD, (sext v2i8:$vB))
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// PowerISA_V3.0:
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do i = 0 to 1
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VR[VRT].dword[i] ← EXTS64(VR[VRB].dword[i].byte[7])
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end
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. vextsh2d
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(set v2i64:$vD, (sext v2i16:$vB))
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// PowerISA_V3.0:
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do i = 0 to 1
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VR[VRT].dword[i] ← EXTS64(VR[VRB].dword[i].hword[3])
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end
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. vextsw2d
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(set v2i64:$vD, (sext v2i32:$vB))
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// PowerISA_V3.0:
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do i = 0 to 1
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VR[VRT].dword[i] ← EXTS64(VR[VRB].dword[i].word[1])
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end
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- Vector Integer Negate: vnegw vnegd
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. Map to llvm ineg
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(set v4i32:$rT, (ineg v4i32:$rA)) // vnegw
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(set v2i64:$rT, (ineg v2i64:$rA)) // vnegd
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- Vector Parity Byte: vprtybw vprtybd vprtybq
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. Use intrinsic:
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(set v4i32:$rD, (int_ppc_altivec_vprtybw v4i32:$vB))
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(set v2i64:$rD, (int_ppc_altivec_vprtybd v2i64:$vB))
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(set v1i128:$rD, (int_ppc_altivec_vprtybq v1i128:$vB))
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- Vector (Bit) Permute (Right-indexed):
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. vbpermd: Same as "vbpermq", use VX1_Int_Ty2:
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VX1_Int_Ty2<1484, "vbpermd", int_ppc_altivec_vbpermd, v2i64, v2i64>;
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. vpermr: use VA1a_Int_Ty3
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VA1a_Int_Ty3<59, "vpermr", int_ppc_altivec_vpermr, v16i8, v16i8, v16i8>;
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- Vector Rotate Left Mask/Mask-Insert: vrlwnm vrlwmi vrldnm vrldmi
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. Use intrinsic:
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VX1_Int_Ty<389, "vrlwnm", int_ppc_altivec_vrlwnm, v4i32>;
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VX1_Int_Ty<133, "vrlwmi", int_ppc_altivec_vrlwmi, v4i32>;
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VX1_Int_Ty<453, "vrldnm", int_ppc_altivec_vrldnm, v2i64>;
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VX1_Int_Ty<197, "vrldmi", int_ppc_altivec_vrldmi, v2i64>;
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- Vector Shift Left/Right: vslv vsrv
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. Use intrinsic, don't map to llvm shl and lshr, because they have different
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semantics, e.g. vslv:
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do i = 0 to 15
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sh ← VR[VRB].byte[i].bit[5:7]
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VR[VRT].byte[i] ← src.byte[i:i+1].bit[sh:sh+7]
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end
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VR[VRT].byte[i] is composed of 2 bytes from src.byte[i:i+1]
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. VX1_Int_Ty<1860, "vslv", int_ppc_altivec_vslv, v16i8>;
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VX1_Int_Ty<1796, "vsrv", int_ppc_altivec_vsrv, v16i8>;
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- Vector Multiply-by-10 (& Write Carry) Unsigned Quadword:
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vmul10uq vmul10cuq
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. Use intrinsic:
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VX1_Int_Ty<513, "vmul10uq", int_ppc_altivec_vmul10uq, v1i128>;
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VX1_Int_Ty< 1, "vmul10cuq", int_ppc_altivec_vmul10cuq, v1i128>;
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- Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword:
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vmul10euq vmul10ecuq
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. Use intrinsic:
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VX1_Int_Ty<577, "vmul10euq", int_ppc_altivec_vmul10euq, v1i128>;
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VX1_Int_Ty< 65, "vmul10ecuq", int_ppc_altivec_vmul10ecuq, v1i128>;
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- Decimal Convert From/to National/Zoned/Signed-QWord:
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bcdcfn. bcdcfz. bcdctn. bcdctz. bcdcfsq. bcdctsq.
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. Use instrinstics:
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(set v1i128:$vD, (int_ppc_altivec_bcdcfno v1i128:$vB, i1:$PS))
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(set v1i128:$vD, (int_ppc_altivec_bcdcfzo v1i128:$vB, i1:$PS))
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(set v1i128:$vD, (int_ppc_altivec_bcdctno v1i128:$vB))
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(set v1i128:$vD, (int_ppc_altivec_bcdctzo v1i128:$vB, i1:$PS))
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(set v1i128:$vD, (int_ppc_altivec_bcdcfsqo v1i128:$vB, i1:$PS))
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(set v1i128:$vD, (int_ppc_altivec_bcdctsqo v1i128:$vB))
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- Decimal Copy-Sign/Set-Sign: bcdcpsgn. bcdsetsgn.
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. Use instrinstics:
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(set v1i128:$vD, (int_ppc_altivec_bcdcpsgno v1i128:$vA, v1i128:$vB))
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(set v1i128:$vD, (int_ppc_altivec_bcdsetsgno v1i128:$vB, i1:$PS))
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- Decimal Shift/Unsigned-Shift/Shift-and-Round: bcds. bcdus. bcdsr.
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. Use instrinstics:
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(set v1i128:$vD, (int_ppc_altivec_bcdso v1i128:$vA, v1i128:$vB, i1:$PS))
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(set v1i128:$vD, (int_ppc_altivec_bcduso v1i128:$vA, v1i128:$vB))
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(set v1i128:$vD, (int_ppc_altivec_bcdsro v1i128:$vA, v1i128:$vB, i1:$PS))
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. Note! Their VA is accessed only 1 byte, i.e. VA.byte[7]
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- Decimal (Unsigned) Truncate: bcdtrunc. bcdutrunc.
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. Use instrinstics:
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(set v1i128:$vD, (int_ppc_altivec_bcdso v1i128:$vA, v1i128:$vB, i1:$PS))
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(set v1i128:$vD, (int_ppc_altivec_bcduso v1i128:$vA, v1i128:$vB))
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. Note! Their VA is accessed only 2 byte, i.e. VA.hword[3] (VA.bit[48:63])
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VSX:
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- QP Copy Sign: xscpsgnqp
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. Similar to xscpsgndp
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. (set f128:$vT, (fcopysign f128:$vB, f128:$vA)
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- QP Absolute/Negative-Absolute/Negate: xsabsqp xsnabsqp xsnegqp
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. Similar to xsabsdp/xsnabsdp/xsnegdp
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. (set f128:$vT, (fabs f128:$vB)) // xsabsqp
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(set f128:$vT, (fneg (fabs f128:$vB))) // xsnabsqp
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(set f128:$vT, (fneg f128:$vB)) // xsnegqp
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- QP Add/Divide/Multiply/Subtract/Square-Root:
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xsaddqp xsdivqp xsmulqp xssubqp xssqrtqp
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. Similar to xsadddp
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. isCommutable = 1
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(set f128:$vT, (fadd f128:$vA, f128:$vB)) // xsaddqp
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(set f128:$vT, (fmul f128:$vA, f128:$vB)) // xsmulqp
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. isCommutable = 0
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(set f128:$vT, (fdiv f128:$vA, f128:$vB)) // xsdivqp
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(set f128:$vT, (fsub f128:$vA, f128:$vB)) // xssubqp
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(set f128:$vT, (fsqrt f128:$vB))) // xssqrtqp
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- Round to Odd of QP Add/Divide/Multiply/Subtract/Square-Root:
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xsaddqpo xsdivqpo xsmulqpo xssubqpo xssqrtqpo
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. Similar to xsrsqrtedp??
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def XSRSQRTEDP : XX2Form<60, 74,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xsrsqrtedp $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (PPCfrsqrte f64:$XB))]>;
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. Define DAG Node in PPCInstrInfo.td:
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def PPCfaddrto: SDNode<"PPCISD::FADDRTO", SDTFPBinOp, []>;
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def PPCfdivrto: SDNode<"PPCISD::FDIVRTO", SDTFPBinOp, []>;
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def PPCfmulrto: SDNode<"PPCISD::FMULRTO", SDTFPBinOp, []>;
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def PPCfsubrto: SDNode<"PPCISD::FSUBRTO", SDTFPBinOp, []>;
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def PPCfsqrtrto: SDNode<"PPCISD::FSQRTRTO", SDTFPUnaryOp, []>;
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DAG patterns of each instruction (PPCInstrVSX.td):
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. isCommutable = 1
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(set f128:$vT, (PPCfaddrto f128:$vA, f128:$vB)) // xsaddqpo
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(set f128:$vT, (PPCfmulrto f128:$vA, f128:$vB)) // xsmulqpo
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. isCommutable = 0
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(set f128:$vT, (PPCfdivrto f128:$vA, f128:$vB)) // xsdivqpo
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(set f128:$vT, (PPCfsubrto f128:$vA, f128:$vB)) // xssubqpo
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(set f128:$vT, (PPCfsqrtrto f128:$vB)) // xssqrtqpo
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- QP (Negative) Multiply-{Add/Subtract}: xsmaddqp xsmsubqp xsnmaddqp xsnmsubqp
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. Ref: xsmaddadp/xsmsubadp/xsnmaddadp/xsnmsubadp
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. isCommutable = 1
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// xsmaddqp
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[(set f128:$vT, (fma f128:$vA, f128:$vB, f128:$vTi))]>,
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RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
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AltVSXFMARel;
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// xsmsubqp
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[(set f128:$vT, (fma f128:$vA, f128:$vB, (fneg f128:$vTi)))]>,
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RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
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AltVSXFMARel;
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// xsnmaddqp
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[(set f128:$vT, (fneg (fma f128:$vA, f128:$vB, f128:$vTi)))]>,
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RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
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AltVSXFMARel;
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// xsnmsubqp
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[(set f128:$vT, (fneg (fma f128:$vA, f128:$vB, (fneg f128:$vTi))))]>,
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RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
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AltVSXFMARel;
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- Round to Odd of QP (Negative) Multiply-{Add/Subtract}:
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xsmaddqpo xsmsubqpo xsnmaddqpo xsnmsubqpo
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. Similar to xsrsqrtedp??
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. Define DAG Node in PPCInstrInfo.td:
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def PPCfmarto: SDNode<"PPCISD::FMARTO", SDTFPTernaryOp, []>;
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It looks like we only need to define "PPCfmarto" for these instructions,
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because according to PowerISA_V3.0, these instructions perform RTO on
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fma's result:
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xsmaddqp(o)
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v ← bfp_MULTIPLY_ADD(src1, src3, src2)
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rnd ← bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v)
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result ← bfp_CONVERT_TO_BFP128(rnd)
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xsmsubqp(o)
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v ← bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
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rnd ← bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v)
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result ← bfp_CONVERT_TO_BFP128(rnd)
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xsnmaddqp(o)
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v ← bfp_MULTIPLY_ADD(src1,src3,src2)
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rnd ← bfp_NEGATE(bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v))
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result ← bfp_CONVERT_TO_BFP128(rnd)
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xsnmsubqp(o)
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v ← bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
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rnd ← bfp_NEGATE(bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v))
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result ← bfp_CONVERT_TO_BFP128(rnd)
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DAG patterns of each instruction (PPCInstrVSX.td):
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. isCommutable = 1
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// xsmaddqpo
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[(set f128:$vT, (PPCfmarto f128:$vA, f128:$vB, f128:$vTi))]>,
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RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
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AltVSXFMARel;
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// xsmsubqpo
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[(set f128:$vT, (PPCfmarto f128:$vA, f128:$vB, (fneg f128:$vTi)))]>,
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RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
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AltVSXFMARel;
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// xsnmaddqpo
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[(set f128:$vT, (fneg (PPCfmarto f128:$vA, f128:$vB, f128:$vTi)))]>,
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RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
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AltVSXFMARel;
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// xsnmsubqpo
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[(set f128:$vT, (fneg (PPCfmarto f128:$vA, f128:$vB, (fneg f128:$vTi))))]>,
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RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
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AltVSXFMARel;
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- QP Compare Ordered/Unordered: xscmpoqp xscmpuqp
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. ref: XSCMPUDP
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def XSCMPUDP : XX3Form_1<60, 35,
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(outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
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"xscmpudp $crD, $XA, $XB", IIC_FPCompare, []>;
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. No SDAG, intrinsic, builtin are required??
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Or llvm fcmp order/unorder compare??
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- DP/QP Compare Exponents: xscmpexpdp xscmpexpqp
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. No SDAG, intrinsic, builtin are required?
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- DP Compare ==, >=, >, !=: xscmpeqdp xscmpgedp xscmpgtdp xscmpnedp
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. I checked existing instruction "XSCMPUDP". They are different in target
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register. "XSCMPUDP" write to CR field, xscmp*dp write to VSX register
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. Use instrinsic:
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(set i128:$XT, (int_ppc_vsx_xscmpeqdp f64:$XA, f64:$XB))
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(set i128:$XT, (int_ppc_vsx_xscmpgedp f64:$XA, f64:$XB))
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(set i128:$XT, (int_ppc_vsx_xscmpgtdp f64:$XA, f64:$XB))
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(set i128:$XT, (int_ppc_vsx_xscmpnedp f64:$XA, f64:$XB))
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- Vector Compare Not Equal: xvcmpnedp xvcmpnedp. xvcmpnesp xvcmpnesp.
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. Similar to xvcmpeqdp:
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defm XVCMPEQDP : XX3Form_Rcr<60, 99,
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"xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare,
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int_ppc_vsx_xvcmpeqdp, v2i64, v2f64>;
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. So we should use "XX3Form_Rcr" to implement instrinsic
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- Convert DP -> QP: xscvdpqp
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. Similar to XSCVDPSP:
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def XSCVDPSP : XX2Form<60, 265,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xscvdpsp $XT, $XB", IIC_VecFP, []>;
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. So, No SDAG, intrinsic, builtin are required??
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- Round & Convert QP -> DP (dword[1] is set to zero): xscvqpdp xscvqpdpo
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. Similar to XSCVDPSP
|
|
. No SDAG, intrinsic, builtin are required??
|
|
|
|
- Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero):
|
|
xscvqpsdz xscvqpswz xscvqpudz xscvqpuwz
|
|
. According to PowerISA_V3.0, these are similar to "XSCVDPSXDS", "XSCVDPSXWS",
|
|
"XSCVDPUXDS", "XSCVDPUXWS"
|
|
|
|
. DAG patterns:
|
|
(set f128:$XT, (PPCfctidz f128:$XB)) // xscvqpsdz
|
|
(set f128:$XT, (PPCfctiwz f128:$XB)) // xscvqpswz
|
|
(set f128:$XT, (PPCfctiduz f128:$XB)) // xscvqpudz
|
|
(set f128:$XT, (PPCfctiwuz f128:$XB)) // xscvqpuwz
|
|
|
|
- Convert (Un)Signed DWord -> QP: xscvsdqp xscvudqp
|
|
. Similar to XSCVSXDSP
|
|
. (set f128:$XT, (PPCfcfids f64:$XB)) // xscvsdqp
|
|
(set f128:$XT, (PPCfcfidus f64:$XB)) // xscvudqp
|
|
|
|
- (Round &) Convert DP <-> HP: xscvdphp xscvhpdp
|
|
. Similar to XSCVDPSP
|
|
. No SDAG, intrinsic, builtin are required??
|
|
|
|
- Vector HP -> SP: xvcvhpsp xvcvsphp
|
|
. Similar to XVCVDPSP:
|
|
def XVCVDPSP : XX2Form<60, 393,
|
|
(outs vsrc:$XT), (ins vsrc:$XB),
|
|
"xvcvdpsp $XT, $XB", IIC_VecFP, []>;
|
|
. No SDAG, intrinsic, builtin are required??
|
|
|
|
- Round to Quad-Precision Integer: xsrqpi xsrqpix
|
|
. These are combination of "XSRDPI", "XSRDPIC", "XSRDPIM", .., because you
|
|
need to assign rounding mode in instruction
|
|
. Provide builtin?
|
|
(set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB))
|
|
(set f128:$vT, (int_ppc_vsx_xsrqpix f128:$vB))
|
|
|
|
- Round Quad-Precision to Double-Extended Precision (fp80): xsrqpxp
|
|
. Provide builtin?
|
|
(set f128:$vT, (int_ppc_vsx_xsrqpxp f128:$vB))
|
|
|
|
Fixed Point Facility:
|
|
|
|
- Exploit cmprb and cmpeqb (perhaps for something like
|
|
isalpha/isdigit/isupper/islower and isspace respectivelly). This can
|
|
perhaps be done through a builtin.
|
|
|
|
- Provide testing for cnttz[dw]
|
|
- Insert Exponent DP/QP: xsiexpdp xsiexpqp
|
|
. Use intrinsic?
|
|
. xsiexpdp:
|
|
// Note: rA and rB are the unsigned integer value.
|
|
(set f128:$XT, (int_ppc_vsx_xsiexpdp i64:$rA, i64:$rB))
|
|
|
|
. xsiexpqp:
|
|
(set f128:$vT, (int_ppc_vsx_xsiexpqp f128:$vA, f64:$vB))
|
|
|
|
- Extract Exponent/Significand DP/QP: xsxexpdp xsxsigdp xsxexpqp xsxsigqp
|
|
. Use intrinsic?
|
|
. (set i64:$rT, (int_ppc_vsx_xsxexpdp f64$XB)) // xsxexpdp
|
|
(set i64:$rT, (int_ppc_vsx_xsxsigdp f64$XB)) // xsxsigdp
|
|
(set f128:$vT, (int_ppc_vsx_xsxexpqp f128$vB)) // xsxexpqp
|
|
(set f128:$vT, (int_ppc_vsx_xsxsigqp f128$vB)) // xsxsigqp
|
|
|
|
- Vector Insert Word: xxinsertw
|
|
- Useful for inserting f32/i32 elements into vectors (the element to be
|
|
inserted needs to be prepared)
|
|
. Note: llvm has insertelem in "Vector Operations"
|
|
; yields <n x <ty>>
|
|
<result> = insertelement <n x <ty>> <val>, <ty> <elt>, <ty2> <idx>
|
|
|
|
But how to map to it??
|
|
[(set v1f128:$XT, (insertelement v1f128:$XTi, f128:$XB, i4:$UIMM))]>,
|
|
RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
|
|
|
|
. Or use intrinsic?
|
|
(set v1f128:$XT, (int_ppc_vsx_xxinsertw v1f128:$XTi, f128:$XB, i4:$UIMM))
|
|
|
|
- Vector Extract Unsigned Word: xxextractuw
|
|
- Not useful for extraction of f32 from v4f32 (the current pattern is better -
|
|
shift->convert)
|
|
- It is useful for (uint_to_fp (vector_extract v4i32, N))
|
|
- Unfortunately, it can't be used for (sint_to_fp (vector_extract v4i32, N))
|
|
. Note: llvm has extractelement in "Vector Operations"
|
|
; yields <ty>
|
|
<result> = extractelement <n x <ty>> <val>, <ty2> <idx>
|
|
|
|
How to map to it??
|
|
[(set f128:$XT, (extractelement v1f128:$XB, i4:$UIMM))]
|
|
|
|
. Or use intrinsic?
|
|
(set f128:$XT, (int_ppc_vsx_xxextractuw v1f128:$XB, i4:$UIMM))
|
|
|
|
- Vector Insert Exponent DP/SP: xviexpdp xviexpsp
|
|
. Use intrinsic
|
|
(set v2f64:$XT, (int_ppc_vsx_xviexpdp v2f64:$XA, v2f64:$XB))
|
|
(set v4f32:$XT, (int_ppc_vsx_xviexpsp v4f32:$XA, v4f32:$XB))
|
|
|
|
- Vector Extract Exponent/Significand DP/SP: xvxexpdp xvxexpsp xvxsigdp xvxsigsp
|
|
. Use intrinsic
|
|
(set v2f64:$XT, (int_ppc_vsx_xvxexpdp v2f64:$XB))
|
|
(set v4f32:$XT, (int_ppc_vsx_xvxexpsp v4f32:$XB))
|
|
(set v2f64:$XT, (int_ppc_vsx_xvxsigdp v2f64:$XB))
|
|
(set v4f32:$XT, (int_ppc_vsx_xvxsigsp v4f32:$XB))
|
|
|
|
- Test Data Class SP/DP/QP: xststdcsp xststdcdp xststdcqp
|
|
. No SDAG, intrinsic, builtin are required?
|
|
Because it seems that we have no way to map BF field?
|
|
|
|
Instruction Form: [PO T XO B XO BX TX]
|
|
Asm: xststd* BF,XB,DCMX
|
|
|
|
BF is an index to CR register field.
|
|
|
|
- Vector Test Data Class SP/DP: xvtstdcsp xvtstdcdp
|
|
. Use intrinsic
|
|
(set v4f32:$XT, (int_ppc_vsx_xvtstdcsp v4f32:$XB, i7:$DCMX))
|
|
(set v2f64:$XT, (int_ppc_vsx_xvtstdcdp v2f64:$XB, i7:$DCMX))
|
|
|
|
- Maximum/Minimum Type-C/Type-J DP: xsmaxcdp xsmaxjdp xsmincdp xsminjdp
|
|
. PowerISA_V3.0:
|
|
"xsmaxcdp can be used to implement the C/C++/Java conditional operation
|
|
(x>y)?x:y for single-precision and double-precision arguments."
|
|
|
|
Note! c type and j type have different behavior when:
|
|
1. Either input is NaN
|
|
2. Both input are +-Infinity, +-Zero
|
|
|
|
. dtype map to llvm fmaxnum/fminnum
|
|
jtype use intrinsic
|
|
|
|
. xsmaxcdp xsmincdp
|
|
(set f64:$XT, (fmaxnum f64:$XA, f64:$XB))
|
|
(set f64:$XT, (fminnum f64:$XA, f64:$XB))
|
|
|
|
. xsmaxjdp xsminjdp
|
|
(set f64:$XT, (int_ppc_vsx_xsmaxjdp f64:$XA, f64:$XB))
|
|
(set f64:$XT, (int_ppc_vsx_xsminjdp f64:$XA, f64:$XB))
|
|
|
|
- Vector Byte-Reverse H/W/D/Q Word: xxbrh xxbrw xxbrd xxbrq
|
|
. Use intrinsic
|
|
(set v8i16:$XT, (int_ppc_vsx_xxbrh v8i16:$XB))
|
|
(set v4i32:$XT, (int_ppc_vsx_xxbrw v4i32:$XB))
|
|
(set v2i64:$XT, (int_ppc_vsx_xxbrd v2i64:$XB))
|
|
(set v1i128:$XT, (int_ppc_vsx_xxbrq v1i128:$XB))
|
|
|
|
- Vector Permute: xxperm xxpermr
|
|
. I have checked "PPCxxswapd" in PPCInstrVSX.td, but they are different
|
|
. Use intrinsic
|
|
(set v16i8:$XT, (int_ppc_vsx_xxperm v16i8:$XA, v16i8:$XB))
|
|
(set v16i8:$XT, (int_ppc_vsx_xxpermr v16i8:$XA, v16i8:$XB))
|
|
|
|
- Vector Splat Immediate Byte: xxspltib
|
|
. Similar to XXSPLTW:
|
|
def XXSPLTW : XX2Form_2<60, 164,
|
|
(outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM),
|
|
"xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>;
|
|
|
|
. No SDAG, intrinsic, builtin are required?
|
|
|
|
- Load/Store Vector: lxv stxv
|
|
. Has likely SDAG match:
|
|
(set v?:$XT, (load ix16addr:$src))
|
|
(set v?:$XT, (store ix16addr:$dst))
|
|
|
|
. Need define ix16addr in PPCInstrInfo.td
|
|
ix16addr: 16-byte aligned, see "def memrix16" in PPCInstrInfo.td
|
|
|
|
- Load/Store Vector Indexed: lxvx stxvx
|
|
. Has likely SDAG match:
|
|
(set v?:$XT, (load xoaddr:$src))
|
|
(set v?:$XT, (store xoaddr:$dst))
|
|
|
|
- Load/Store DWord: lxsd stxsd
|
|
. Similar to lxsdx/stxsdx:
|
|
def LXSDX : XX1Form<31, 588,
|
|
(outs vsfrc:$XT), (ins memrr:$src),
|
|
"lxsdx $XT, $src", IIC_LdStLFD,
|
|
[(set f64:$XT, (load xoaddr:$src))]>;
|
|
|
|
. (set f64:$XT, (load ixaddr:$src))
|
|
(set f64:$XT, (store ixaddr:$dst))
|
|
|
|
- Load/Store SP, with conversion from/to DP: lxssp stxssp
|
|
. Similar to lxsspx/stxsspx:
|
|
def LXSSPX : XX1Form<31, 524, (outs vssrc:$XT), (ins memrr:$src),
|
|
"lxsspx $XT, $src", IIC_LdStLFD,
|
|
[(set f32:$XT, (load xoaddr:$src))]>;
|
|
|
|
. (set f32:$XT, (load ixaddr:$src))
|
|
(set f32:$XT, (store ixaddr:$dst))
|
|
|
|
- Load as Integer Byte/Halfword & Zero Indexed: lxsibzx lxsihzx
|
|
. Similar to lxsiwzx:
|
|
def LXSIWZX : XX1Form<31, 12, (outs vsfrc:$XT), (ins memrr:$src),
|
|
"lxsiwzx $XT, $src", IIC_LdStLFD,
|
|
[(set f64:$XT, (PPClfiwzx xoaddr:$src))]>;
|
|
|
|
. (set f64:$XT, (PPClfiwzx xoaddr:$src))
|
|
|
|
- Store as Integer Byte/Halfword Indexed: stxsibx stxsihx
|
|
. Similar to stxsiwx:
|
|
def STXSIWX : XX1Form<31, 140, (outs), (ins vsfrc:$XT, memrr:$dst),
|
|
"stxsiwx $XT, $dst", IIC_LdStSTFD,
|
|
[(PPCstfiwx f64:$XT, xoaddr:$dst)]>;
|
|
|
|
. (PPCstfiwx f64:$XT, xoaddr:$dst)
|
|
|
|
- Load Vector Halfword*8/Byte*16 Indexed: lxvh8x lxvb16x
|
|
. Similar to lxvd2x/lxvw4x:
|
|
def LXVD2X : XX1Form<31, 844,
|
|
(outs vsrc:$XT), (ins memrr:$src),
|
|
"lxvd2x $XT, $src", IIC_LdStLFD,
|
|
[(set v2f64:$XT, (int_ppc_vsx_lxvd2x xoaddr:$src))]>;
|
|
|
|
. (set v8i16:$XT, (int_ppc_vsx_lxvh8x xoaddr:$src))
|
|
(set v16i8:$XT, (int_ppc_vsx_lxvb16x xoaddr:$src))
|
|
|
|
- Store Vector Halfword*8/Byte*16 Indexed: stxvh8x stxvb16x
|
|
. Similar to stxvd2x/stxvw4x:
|
|
def STXVD2X : XX1Form<31, 972,
|
|
(outs), (ins vsrc:$XT, memrr:$dst),
|
|
"stxvd2x $XT, $dst", IIC_LdStSTFD,
|
|
[(store v2f64:$XT, xoaddr:$dst)]>;
|
|
|
|
. (store v8i16:$XT, xoaddr:$dst)
|
|
(store v16i8:$XT, xoaddr:$dst)
|
|
|
|
- Load/Store Vector (Left-justified) with Length: lxvl lxvll stxvl stxvll
|
|
. Likely needs an intrinsic
|
|
. (set v?:$XT, (int_ppc_vsx_lxvl xoaddr:$src))
|
|
(set v?:$XT, (int_ppc_vsx_lxvll xoaddr:$src))
|
|
|
|
. (int_ppc_vsx_stxvl xoaddr:$dst))
|
|
(int_ppc_vsx_stxvll xoaddr:$dst))
|
|
|
|
- Load Vector Word & Splat Indexed: lxvwsx
|
|
. Likely needs an intrinsic
|
|
. (set v?:$XT, (int_ppc_vsx_lxvwsx xoaddr:$src))
|
|
|
|
Atomic operations (l[dw]at, st[dw]at):
|
|
- Provide custom lowering for common atomic operations to use these
|
|
instructions with the correct Function Code
|
|
- Ensure the operands are in the correct register (i.e. RT+1, RT+2)
|
|
- Provide builtins since not all FC's necessarily have an existing LLVM
|
|
atomic operation
|
|
|
|
Load Doubleword Monitored (ldmx):
|
|
- Investigate whether there are any uses for this. It seems to be related to
|
|
Garbage Collection so it isn't likely to be all that useful for most
|
|
languages we deal with.
|
|
|
|
Move to CR from XER Extended (mcrxrx):
|
|
- Is there a use for this in LLVM?
|
|
|
|
Fixed Point Facility:
|
|
|
|
- Copy-Paste Facility: copy copy_first cp_abort paste paste. paste_last
|
|
. Use instrinstics:
|
|
(int_ppc_copy_first i32:$rA, i32:$rB)
|
|
(int_ppc_copy i32:$rA, i32:$rB)
|
|
|
|
(int_ppc_paste i32:$rA, i32:$rB)
|
|
(int_ppc_paste_last i32:$rA, i32:$rB)
|
|
|
|
(int_cp_abort)
|
|
|
|
- Message Synchronize: msgsync
|
|
- SLB*: slbieg slbsync
|
|
- stop
|
|
. No instrinstics
|