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https://github.com/RPCSX/llvm.git
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ed541fe200
Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250407 91177308-0d34-0410-b5e6-96231b3b80d8
76 lines
2.5 KiB
LLVM
76 lines
2.5 KiB
LLVM
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@iiii = global i32 25, align 4
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@jjjj = global i32 35, align 4
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@kkkk = global i32 100, align 4
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@t = global i32 25, align 4
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@riii = common global i32 0, align 4
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@rjjj = common global i32 0, align 4
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@rkkk = common global i32 0, align 4
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define void @temp(i32 %foo) nounwind {
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entry:
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%foo.addr = alloca i32, align 4
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store i32 %foo, i32* %foo.addr, align 4
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%0 = load i32, i32* %foo.addr, align 4
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store i32 %0, i32* @t, align 4
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ret void
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}
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define void @test() nounwind {
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entry:
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; 16: .frame $sp,8,$ra
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; 16: save 8 # 16 bit inst
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; 16: move $16, $sp
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; 16: move ${{[0-9]+}}, $sp
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; 16: subu $[[REGISTER:[0-9]+]], ${{[0-9]+}}, ${{[0-9]+}}
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; 16: move $sp, $[[REGISTER]]
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%sssi = alloca i32, align 4
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%ip = alloca i32*, align 4
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%sssj = alloca i32, align 4
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%0 = load i32, i32* @iiii, align 4
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store i32 %0, i32* %sssi, align 4
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%1 = load i32, i32* @kkkk, align 4
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%mul = mul nsw i32 %1, 100
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%2 = alloca i8, i32 %mul
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%3 = bitcast i8* %2 to i32*
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store i32* %3, i32** %ip, align 4
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%4 = load i32, i32* @jjjj, align 4
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store i32 %4, i32* %sssj, align 4
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%5 = load i32, i32* @jjjj, align 4
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%6 = load i32, i32* @iiii, align 4
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%7 = load i32*, i32** %ip, align 4
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%arrayidx = getelementptr inbounds i32, i32* %7, i32 %6
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store i32 %5, i32* %arrayidx, align 4
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%8 = load i32, i32* @kkkk, align 4
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%9 = load i32, i32* @jjjj, align 4
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%10 = load i32*, i32** %ip, align 4
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%arrayidx1 = getelementptr inbounds i32, i32* %10, i32 %9
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store i32 %8, i32* %arrayidx1, align 4
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%11 = load i32, i32* @iiii, align 4
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%12 = load i32, i32* @kkkk, align 4
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%13 = load i32*, i32** %ip, align 4
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%arrayidx2 = getelementptr inbounds i32, i32* %13, i32 %12
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store i32 %11, i32* %arrayidx2, align 4
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%14 = load i32*, i32** %ip, align 4
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%arrayidx3 = getelementptr inbounds i32, i32* %14, i32 25
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%15 = load i32, i32* %arrayidx3, align 4
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store i32 %15, i32* @riii, align 4
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%16 = load i32*, i32** %ip, align 4
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%arrayidx4 = getelementptr inbounds i32, i32* %16, i32 35
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%17 = load i32, i32* %arrayidx4, align 4
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store i32 %17, i32* @rjjj, align 4
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%18 = load i32*, i32** %ip, align 4
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%arrayidx5 = getelementptr inbounds i32, i32* %18, i32 100
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%19 = load i32, i32* %arrayidx5, align 4
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store i32 %19, i32* @rkkk, align 4
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%20 = load i32, i32* @t, align 4
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%21 = load i32*, i32** %ip, align 4
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%arrayidx6 = getelementptr inbounds i32, i32* %21, i32 %20
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%22 = load i32, i32* %arrayidx6, align 4
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; 16: addiu $sp, -16
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call void @temp(i32 %22)
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; 16: addiu $sp, 16
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ret void
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}
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