mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-13 23:18:51 +00:00
354362524a
This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
91 lines
2.6 KiB
C++
91 lines
2.6 KiB
C++
//===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file implements the Hexagon specific subclass of TargetSubtarget.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "HexagonSubtarget.h"
|
|
#include "Hexagon.h"
|
|
#include "HexagonRegisterInfo.h"
|
|
#include "llvm/Support/CommandLine.h"
|
|
#include "llvm/Support/ErrorHandling.h"
|
|
using namespace llvm;
|
|
|
|
#define GET_SUBTARGETINFO_CTOR
|
|
#define GET_SUBTARGETINFO_TARGET_DESC
|
|
#include "HexagonGenSubtargetInfo.inc"
|
|
|
|
static cl::opt<bool>
|
|
EnableV3("enable-hexagon-v3", cl::Hidden,
|
|
cl::desc("Enable Hexagon V3 instructions."));
|
|
|
|
static cl::opt<bool>
|
|
EnableMemOps(
|
|
"enable-hexagon-memops",
|
|
cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(true),
|
|
cl::desc(
|
|
"Generate V4 MEMOP in code generation for Hexagon target"));
|
|
|
|
static cl::opt<bool>
|
|
DisableMemOps(
|
|
"disable-hexagon-memops",
|
|
cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(false),
|
|
cl::desc(
|
|
"Do not generate V4 MEMOP in code generation for Hexagon target"));
|
|
|
|
static cl::opt<bool>
|
|
EnableIEEERndNear(
|
|
"enable-hexagon-ieee-rnd-near",
|
|
cl::Hidden, cl::ZeroOrMore, cl::init(false),
|
|
cl::desc("Generate non-chopped conversion from fp to int."));
|
|
|
|
HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS):
|
|
HexagonGenSubtargetInfo(TT, CPU, FS),
|
|
CPUString(CPU.str()) {
|
|
|
|
// If the programmer has not specified a Hexagon version, default to -mv4.
|
|
if (CPUString.empty())
|
|
CPUString = "hexagonv4";
|
|
|
|
if (CPUString == "hexagonv2") {
|
|
HexagonArchVersion = V2;
|
|
} else if (CPUString == "hexagonv3") {
|
|
EnableV3 = true;
|
|
HexagonArchVersion = V3;
|
|
} else if (CPUString == "hexagonv4") {
|
|
HexagonArchVersion = V4;
|
|
} else if (CPUString == "hexagonv5") {
|
|
HexagonArchVersion = V5;
|
|
} else {
|
|
llvm_unreachable("Unrecognized Hexagon processor version");
|
|
}
|
|
|
|
ParseSubtargetFeatures(CPUString, FS);
|
|
|
|
// Initialize scheduling itinerary for the specified CPU.
|
|
InstrItins = getInstrItineraryForCPU(CPUString);
|
|
|
|
// UseMemOps on by default unless disabled explicitly
|
|
if (DisableMemOps)
|
|
UseMemOps = false;
|
|
else if (EnableMemOps)
|
|
UseMemOps = true;
|
|
else
|
|
UseMemOps = false;
|
|
|
|
if (EnableIEEERndNear)
|
|
ModeIEEERndNear = true;
|
|
else
|
|
ModeIEEERndNear = false;
|
|
}
|
|
|
|
// Pin the vtable to this file.
|
|
void HexagonSubtarget::anchor() {}
|