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2a04c76ecd
This commit serializes the UsedPhysRegMask register mask from the machine register information class. The mask is serialized as an inverted 'calleeSavedRegisters' mask to keep the output minimal. This commit also allows the MIR parser to infer this mask from the register mask operands if the machine function doesn't specify it. Reviewers: Duncan P. N. Exon Smith git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244548 91177308-0d34-0410-b5e6-96231b3b80d8
772 lines
25 KiB
C++
772 lines
25 KiB
C++
//===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the class that prints out the LLVM IR and machine
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// functions using the MIR serialization format.
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//
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//===----------------------------------------------------------------------===//
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#include "MIRPrinter.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MIRYamlMapping.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/IRPrintingPasses.h"
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#include "llvm/IR/Module.h"
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#include "llvm/IR/ModuleSlotTracker.h"
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#include "llvm/Support/MemoryBuffer.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/YAMLTraits.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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namespace {
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/// This structure describes how to print out stack object references.
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struct FrameIndexOperand {
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std::string Name;
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unsigned ID;
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bool IsFixed;
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FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
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: Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
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/// Return an ordinary stack object reference.
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static FrameIndexOperand create(StringRef Name, unsigned ID) {
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return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
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}
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/// Return a fixed stack object reference.
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static FrameIndexOperand createFixed(unsigned ID) {
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return FrameIndexOperand("", ID, /*IsFixed=*/true);
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}
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};
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} // end anonymous namespace
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namespace llvm {
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/// This class prints out the machine functions using the MIR serialization
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/// format.
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class MIRPrinter {
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raw_ostream &OS;
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DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
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/// Maps from stack object indices to operand indices which will be used when
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/// printing frame index machine operands.
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DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
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public:
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MIRPrinter(raw_ostream &OS) : OS(OS) {}
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void print(const MachineFunction &MF);
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void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
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const TargetRegisterInfo *TRI);
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void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
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const MachineFrameInfo &MFI);
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void convert(yaml::MachineFunction &MF,
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const MachineConstantPool &ConstantPool);
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void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
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const MachineJumpTableInfo &JTI);
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void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
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const MachineBasicBlock &MBB);
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void convertStackObjects(yaml::MachineFunction &MF,
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const MachineFrameInfo &MFI,
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const TargetRegisterInfo *TRI);
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private:
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void initRegisterMaskIds(const MachineFunction &MF);
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};
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} // end namespace llvm
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namespace {
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/// This class prints out the machine instructions using the MIR serialization
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/// format.
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class MIPrinter {
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raw_ostream &OS;
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ModuleSlotTracker &MST;
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const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
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const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
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public:
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MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
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const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
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const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
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: OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
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StackObjectOperandMapping(StackObjectOperandMapping) {}
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void print(const MachineInstr &MI);
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void printMBBReference(const MachineBasicBlock &MBB);
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void printIRBlockReference(const BasicBlock &BB);
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void printIRValueReference(const Value &V);
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void printStackObjectReference(int FrameIndex);
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void printOffset(int64_t Offset);
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void printTargetFlags(const MachineOperand &Op);
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void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
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void print(const MachineMemOperand &Op);
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void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
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};
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} // end anonymous namespace
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namespace llvm {
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namespace yaml {
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/// This struct serializes the LLVM IR module.
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template <> struct BlockScalarTraits<Module> {
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static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
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Mod.print(OS, nullptr);
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}
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static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
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llvm_unreachable("LLVM Module is supposed to be parsed separately");
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return "";
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}
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};
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} // end namespace yaml
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} // end namespace llvm
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static void printReg(unsigned Reg, raw_ostream &OS,
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const TargetRegisterInfo *TRI) {
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// TODO: Print Stack Slots.
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if (!Reg)
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OS << '_';
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else if (TargetRegisterInfo::isVirtualRegister(Reg))
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OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
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else if (Reg < TRI->getNumRegs())
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OS << '%' << StringRef(TRI->getName(Reg)).lower();
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else
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llvm_unreachable("Can't print this kind of register yet");
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}
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static void printReg(unsigned Reg, yaml::StringValue &Dest,
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const TargetRegisterInfo *TRI) {
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raw_string_ostream OS(Dest.Value);
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printReg(Reg, OS, TRI);
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}
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void MIRPrinter::print(const MachineFunction &MF) {
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initRegisterMaskIds(MF);
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yaml::MachineFunction YamlMF;
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YamlMF.Name = MF.getName();
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YamlMF.Alignment = MF.getAlignment();
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YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
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YamlMF.HasInlineAsm = MF.hasInlineAsm();
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convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
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ModuleSlotTracker MST(MF.getFunction()->getParent());
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MST.incorporateFunction(*MF.getFunction());
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convert(MST, YamlMF.FrameInfo, *MF.getFrameInfo());
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convertStackObjects(YamlMF, *MF.getFrameInfo(),
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MF.getSubtarget().getRegisterInfo());
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if (const auto *ConstantPool = MF.getConstantPool())
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convert(YamlMF, *ConstantPool);
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if (const auto *JumpTableInfo = MF.getJumpTableInfo())
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convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
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for (const auto &MBB : MF) {
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yaml::MachineBasicBlock YamlMBB;
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convert(MST, YamlMBB, MBB);
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YamlMF.BasicBlocks.push_back(YamlMBB);
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}
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yaml::Output Out(OS);
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Out << YamlMF;
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}
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void MIRPrinter::convert(yaml::MachineFunction &MF,
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const MachineRegisterInfo &RegInfo,
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const TargetRegisterInfo *TRI) {
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MF.IsSSA = RegInfo.isSSA();
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MF.TracksRegLiveness = RegInfo.tracksLiveness();
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MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
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// Print the virtual register definitions.
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for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
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yaml::VirtualRegisterDefinition VReg;
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VReg.ID = I;
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VReg.Class =
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StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
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unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
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if (PreferredReg)
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printReg(PreferredReg, VReg.PreferredRegister, TRI);
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MF.VirtualRegisters.push_back(VReg);
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}
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// Print the live ins.
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for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) {
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yaml::MachineFunctionLiveIn LiveIn;
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printReg(I->first, LiveIn.Register, TRI);
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if (I->second)
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printReg(I->second, LiveIn.VirtualRegister, TRI);
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MF.LiveIns.push_back(LiveIn);
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}
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// The used physical register mask is printed as an inverted callee saved
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// register mask.
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const BitVector &UsedPhysRegMask = RegInfo.getUsedPhysRegsMask();
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if (UsedPhysRegMask.none())
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return;
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std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
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for (unsigned I = 0, E = UsedPhysRegMask.size(); I != E; ++I) {
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if (!UsedPhysRegMask[I]) {
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yaml::FlowStringValue Reg;
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printReg(I, Reg, TRI);
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CalleeSavedRegisters.push_back(Reg);
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}
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}
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MF.CalleeSavedRegisters = CalleeSavedRegisters;
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}
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void MIRPrinter::convert(ModuleSlotTracker &MST,
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yaml::MachineFrameInfo &YamlMFI,
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const MachineFrameInfo &MFI) {
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YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
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YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
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YamlMFI.HasStackMap = MFI.hasStackMap();
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YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
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YamlMFI.StackSize = MFI.getStackSize();
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YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
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YamlMFI.MaxAlignment = MFI.getMaxAlignment();
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YamlMFI.AdjustsStack = MFI.adjustsStack();
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YamlMFI.HasCalls = MFI.hasCalls();
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YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
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YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
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YamlMFI.HasVAStart = MFI.hasVAStart();
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YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
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if (MFI.getSavePoint()) {
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raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
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MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
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.printMBBReference(*MFI.getSavePoint());
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}
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if (MFI.getRestorePoint()) {
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raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
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MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
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.printMBBReference(*MFI.getRestorePoint());
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}
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}
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void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF,
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const MachineFrameInfo &MFI,
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const TargetRegisterInfo *TRI) {
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// Process fixed stack objects.
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unsigned ID = 0;
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for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
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if (MFI.isDeadObjectIndex(I))
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continue;
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yaml::FixedMachineStackObject YamlObject;
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YamlObject.ID = ID;
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YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
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? yaml::FixedMachineStackObject::SpillSlot
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: yaml::FixedMachineStackObject::DefaultType;
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YamlObject.Offset = MFI.getObjectOffset(I);
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YamlObject.Size = MFI.getObjectSize(I);
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YamlObject.Alignment = MFI.getObjectAlignment(I);
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YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
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YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
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MF.FixedStackObjects.push_back(YamlObject);
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StackObjectOperandMapping.insert(
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std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
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}
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// Process ordinary stack objects.
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ID = 0;
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for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
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if (MFI.isDeadObjectIndex(I))
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continue;
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yaml::MachineStackObject YamlObject;
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YamlObject.ID = ID;
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if (const auto *Alloca = MFI.getObjectAllocation(I))
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YamlObject.Name.Value =
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Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
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YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
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? yaml::MachineStackObject::SpillSlot
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: MFI.isVariableSizedObjectIndex(I)
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? yaml::MachineStackObject::VariableSized
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: yaml::MachineStackObject::DefaultType;
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YamlObject.Offset = MFI.getObjectOffset(I);
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YamlObject.Size = MFI.getObjectSize(I);
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YamlObject.Alignment = MFI.getObjectAlignment(I);
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MF.StackObjects.push_back(YamlObject);
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StackObjectOperandMapping.insert(std::make_pair(
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I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
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}
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for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
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yaml::StringValue Reg;
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printReg(CSInfo.getReg(), Reg, TRI);
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auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
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assert(StackObjectInfo != StackObjectOperandMapping.end() &&
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"Invalid stack object index");
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const FrameIndexOperand &StackObject = StackObjectInfo->second;
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if (StackObject.IsFixed)
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MF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
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else
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MF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
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}
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}
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void MIRPrinter::convert(yaml::MachineFunction &MF,
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const MachineConstantPool &ConstantPool) {
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unsigned ID = 0;
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for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
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// TODO: Serialize target specific constant pool entries.
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if (Constant.isMachineConstantPoolEntry())
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llvm_unreachable("Can't print target specific constant pool entries yet");
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yaml::MachineConstantPoolValue YamlConstant;
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std::string Str;
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raw_string_ostream StrOS(Str);
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Constant.Val.ConstVal->printAsOperand(StrOS);
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YamlConstant.ID = ID++;
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YamlConstant.Value = StrOS.str();
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YamlConstant.Alignment = Constant.getAlignment();
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MF.Constants.push_back(YamlConstant);
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}
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}
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void MIRPrinter::convert(ModuleSlotTracker &MST,
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yaml::MachineJumpTable &YamlJTI,
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const MachineJumpTableInfo &JTI) {
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YamlJTI.Kind = JTI.getEntryKind();
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unsigned ID = 0;
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for (const auto &Table : JTI.getJumpTables()) {
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std::string Str;
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yaml::MachineJumpTable::Entry Entry;
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Entry.ID = ID++;
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for (const auto *MBB : Table.MBBs) {
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raw_string_ostream StrOS(Str);
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MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
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.printMBBReference(*MBB);
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Entry.Blocks.push_back(StrOS.str());
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Str.clear();
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}
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YamlJTI.Entries.push_back(Entry);
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}
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}
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void MIRPrinter::convert(ModuleSlotTracker &MST,
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yaml::MachineBasicBlock &YamlMBB,
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const MachineBasicBlock &MBB) {
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assert(MBB.getNumber() >= 0 && "Invalid MBB number");
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YamlMBB.ID = (unsigned)MBB.getNumber();
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if (const auto *BB = MBB.getBasicBlock()) {
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if (BB->hasName()) {
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YamlMBB.Name.Value = BB->getName();
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} else {
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int Slot = MST.getLocalSlot(BB);
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if (Slot == -1)
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YamlMBB.IRBlock.Value = "<badref>";
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else
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YamlMBB.IRBlock.Value = (Twine("%ir-block.") + Twine(Slot)).str();
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}
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}
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YamlMBB.Alignment = MBB.getAlignment();
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YamlMBB.AddressTaken = MBB.hasAddressTaken();
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YamlMBB.IsLandingPad = MBB.isLandingPad();
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for (const auto *SuccMBB : MBB.successors()) {
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std::string Str;
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raw_string_ostream StrOS(Str);
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MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
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.printMBBReference(*SuccMBB);
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YamlMBB.Successors.push_back(StrOS.str());
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}
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if (MBB.hasSuccessorWeights()) {
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for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I)
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YamlMBB.SuccessorWeights.push_back(
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yaml::UnsignedValue(MBB.getSuccWeight(I)));
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}
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// Print the live in registers.
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const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
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assert(TRI && "Expected target register info");
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for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
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std::string Str;
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raw_string_ostream StrOS(Str);
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printReg(*I, StrOS, TRI);
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YamlMBB.LiveIns.push_back(StrOS.str());
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}
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// Print the machine instructions.
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YamlMBB.Instructions.reserve(MBB.size());
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std::string Str;
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for (const auto &MI : MBB) {
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raw_string_ostream StrOS(Str);
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MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping).print(MI);
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YamlMBB.Instructions.push_back(StrOS.str());
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Str.clear();
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}
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}
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void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
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const auto *TRI = MF.getSubtarget().getRegisterInfo();
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unsigned I = 0;
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for (const uint32_t *Mask : TRI->getRegMasks())
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RegisterMaskIds.insert(std::make_pair(Mask, I++));
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}
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void MIPrinter::print(const MachineInstr &MI) {
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const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
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const auto *TRI = SubTarget.getRegisterInfo();
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assert(TRI && "Expected target register info");
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const auto *TII = SubTarget.getInstrInfo();
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assert(TII && "Expected target instruction info");
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if (MI.isCFIInstruction())
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assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
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unsigned I = 0, E = MI.getNumOperands();
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for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
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!MI.getOperand(I).isImplicit();
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++I) {
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if (I)
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OS << ", ";
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print(MI.getOperand(I), TRI);
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}
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if (I)
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OS << " = ";
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if (MI.getFlag(MachineInstr::FrameSetup))
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OS << "frame-setup ";
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OS << TII->getName(MI.getOpcode());
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// TODO: Print the bundling instruction flags.
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if (I < E)
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OS << ' ';
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|
bool NeedComma = false;
|
|
for (; I < E; ++I) {
|
|
if (NeedComma)
|
|
OS << ", ";
|
|
print(MI.getOperand(I), TRI);
|
|
NeedComma = true;
|
|
}
|
|
|
|
if (MI.getDebugLoc()) {
|
|
if (NeedComma)
|
|
OS << ',';
|
|
OS << " debug-location ";
|
|
MI.getDebugLoc()->printAsOperand(OS, MST);
|
|
}
|
|
|
|
if (!MI.memoperands_empty()) {
|
|
OS << " :: ";
|
|
bool NeedComma = false;
|
|
for (const auto *Op : MI.memoperands()) {
|
|
if (NeedComma)
|
|
OS << ", ";
|
|
print(*Op);
|
|
NeedComma = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
|
|
OS << "%bb." << MBB.getNumber();
|
|
if (const auto *BB = MBB.getBasicBlock()) {
|
|
if (BB->hasName())
|
|
OS << '.' << BB->getName();
|
|
}
|
|
}
|
|
|
|
void MIPrinter::printIRBlockReference(const BasicBlock &BB) {
|
|
OS << "%ir-block.";
|
|
if (BB.hasName()) {
|
|
printLLVMNameWithoutPrefix(OS, BB.getName());
|
|
return;
|
|
}
|
|
const Function *F = BB.getParent();
|
|
int Slot;
|
|
if (F == MST.getCurrentFunction()) {
|
|
Slot = MST.getLocalSlot(&BB);
|
|
} else {
|
|
ModuleSlotTracker CustomMST(F->getParent(),
|
|
/*ShouldInitializeAllMetadata=*/false);
|
|
CustomMST.incorporateFunction(*F);
|
|
Slot = CustomMST.getLocalSlot(&BB);
|
|
}
|
|
if (Slot == -1)
|
|
OS << "<badref>";
|
|
else
|
|
OS << Slot;
|
|
}
|
|
|
|
void MIPrinter::printIRValueReference(const Value &V) {
|
|
OS << "%ir.";
|
|
if (V.hasName()) {
|
|
printLLVMNameWithoutPrefix(OS, V.getName());
|
|
return;
|
|
}
|
|
// TODO: Serialize the unnamed IR value references.
|
|
OS << "<unserializable ir value>";
|
|
}
|
|
|
|
void MIPrinter::printStackObjectReference(int FrameIndex) {
|
|
auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
|
|
assert(ObjectInfo != StackObjectOperandMapping.end() &&
|
|
"Invalid frame index");
|
|
const FrameIndexOperand &Operand = ObjectInfo->second;
|
|
if (Operand.IsFixed) {
|
|
OS << "%fixed-stack." << Operand.ID;
|
|
return;
|
|
}
|
|
OS << "%stack." << Operand.ID;
|
|
if (!Operand.Name.empty())
|
|
OS << '.' << Operand.Name;
|
|
}
|
|
|
|
void MIPrinter::printOffset(int64_t Offset) {
|
|
if (Offset == 0)
|
|
return;
|
|
if (Offset < 0) {
|
|
OS << " - " << -Offset;
|
|
return;
|
|
}
|
|
OS << " + " << Offset;
|
|
}
|
|
|
|
static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
|
|
auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
|
|
for (const auto &I : Flags) {
|
|
if (I.first == TF) {
|
|
return I.second;
|
|
}
|
|
}
|
|
return nullptr;
|
|
}
|
|
|
|
void MIPrinter::printTargetFlags(const MachineOperand &Op) {
|
|
if (!Op.getTargetFlags())
|
|
return;
|
|
const auto *TII =
|
|
Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo();
|
|
assert(TII && "expected instruction info");
|
|
auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
|
|
OS << "target-flags(";
|
|
if (const auto *Name = getTargetFlagName(TII, Flags.first))
|
|
OS << Name;
|
|
else
|
|
OS << "<unknown target flag>";
|
|
// TODO: Print the target's bit flags.
|
|
OS << ") ";
|
|
}
|
|
|
|
static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
|
|
const auto *TII = MF.getSubtarget().getInstrInfo();
|
|
assert(TII && "expected instruction info");
|
|
auto Indices = TII->getSerializableTargetIndices();
|
|
for (const auto &I : Indices) {
|
|
if (I.first == Index) {
|
|
return I.second;
|
|
}
|
|
}
|
|
return nullptr;
|
|
}
|
|
|
|
void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
|
|
printTargetFlags(Op);
|
|
switch (Op.getType()) {
|
|
case MachineOperand::MO_Register:
|
|
// TODO: Print the other register flags.
|
|
if (Op.isImplicit())
|
|
OS << (Op.isDef() ? "implicit-def " : "implicit ");
|
|
if (Op.isDead())
|
|
OS << "dead ";
|
|
if (Op.isKill())
|
|
OS << "killed ";
|
|
if (Op.isUndef())
|
|
OS << "undef ";
|
|
if (Op.isEarlyClobber())
|
|
OS << "early-clobber ";
|
|
if (Op.isDebug())
|
|
OS << "debug-use ";
|
|
printReg(Op.getReg(), OS, TRI);
|
|
// Print the sub register.
|
|
if (Op.getSubReg() != 0)
|
|
OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
|
|
break;
|
|
case MachineOperand::MO_Immediate:
|
|
OS << Op.getImm();
|
|
break;
|
|
case MachineOperand::MO_CImmediate:
|
|
Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
|
|
break;
|
|
case MachineOperand::MO_FPImmediate:
|
|
Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
|
|
break;
|
|
case MachineOperand::MO_MachineBasicBlock:
|
|
printMBBReference(*Op.getMBB());
|
|
break;
|
|
case MachineOperand::MO_FrameIndex:
|
|
printStackObjectReference(Op.getIndex());
|
|
break;
|
|
case MachineOperand::MO_ConstantPoolIndex:
|
|
OS << "%const." << Op.getIndex();
|
|
printOffset(Op.getOffset());
|
|
break;
|
|
case MachineOperand::MO_TargetIndex: {
|
|
OS << "target-index(";
|
|
if (const auto *Name = getTargetIndexName(
|
|
*Op.getParent()->getParent()->getParent(), Op.getIndex()))
|
|
OS << Name;
|
|
else
|
|
OS << "<unknown>";
|
|
OS << ')';
|
|
printOffset(Op.getOffset());
|
|
break;
|
|
}
|
|
case MachineOperand::MO_JumpTableIndex:
|
|
OS << "%jump-table." << Op.getIndex();
|
|
break;
|
|
case MachineOperand::MO_ExternalSymbol:
|
|
OS << '$';
|
|
printLLVMNameWithoutPrefix(OS, Op.getSymbolName());
|
|
printOffset(Op.getOffset());
|
|
break;
|
|
case MachineOperand::MO_GlobalAddress:
|
|
Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
|
|
printOffset(Op.getOffset());
|
|
break;
|
|
case MachineOperand::MO_BlockAddress:
|
|
OS << "blockaddress(";
|
|
Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
|
|
MST);
|
|
OS << ", ";
|
|
printIRBlockReference(*Op.getBlockAddress()->getBasicBlock());
|
|
OS << ')';
|
|
printOffset(Op.getOffset());
|
|
break;
|
|
case MachineOperand::MO_RegisterMask: {
|
|
auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
|
|
if (RegMaskInfo != RegisterMaskIds.end())
|
|
OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
|
|
else
|
|
llvm_unreachable("Can't print this machine register mask yet.");
|
|
break;
|
|
}
|
|
case MachineOperand::MO_RegisterLiveOut: {
|
|
const uint32_t *RegMask = Op.getRegLiveOut();
|
|
OS << "liveout(";
|
|
bool IsCommaNeeded = false;
|
|
for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
|
|
if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
|
|
if (IsCommaNeeded)
|
|
OS << ", ";
|
|
printReg(Reg, OS, TRI);
|
|
IsCommaNeeded = true;
|
|
}
|
|
}
|
|
OS << ")";
|
|
break;
|
|
}
|
|
case MachineOperand::MO_Metadata:
|
|
Op.getMetadata()->printAsOperand(OS, MST);
|
|
break;
|
|
case MachineOperand::MO_CFIIndex: {
|
|
const auto &MMI = Op.getParent()->getParent()->getParent()->getMMI();
|
|
print(MMI.getFrameInstructions()[Op.getCFIIndex()], TRI);
|
|
break;
|
|
}
|
|
default:
|
|
// TODO: Print the other machine operands.
|
|
llvm_unreachable("Can't print this machine operand at the moment");
|
|
}
|
|
}
|
|
|
|
void MIPrinter::print(const MachineMemOperand &Op) {
|
|
OS << '(';
|
|
// TODO: Print operand's target specific flags.
|
|
if (Op.isVolatile())
|
|
OS << "volatile ";
|
|
if (Op.isNonTemporal())
|
|
OS << "non-temporal ";
|
|
if (Op.isInvariant())
|
|
OS << "invariant ";
|
|
if (Op.isLoad())
|
|
OS << "load ";
|
|
else {
|
|
assert(Op.isStore() && "Non load machine operand must be a store");
|
|
OS << "store ";
|
|
}
|
|
OS << Op.getSize() << (Op.isLoad() ? " from " : " into ");
|
|
if (const Value *Val = Op.getValue())
|
|
printIRValueReference(*Val);
|
|
// TODO: Print PseudoSourceValue.
|
|
printOffset(Op.getOffset());
|
|
if (Op.getBaseAlignment() != Op.getSize())
|
|
OS << ", align " << Op.getBaseAlignment();
|
|
// TODO: Print the metadata attributes.
|
|
OS << ')';
|
|
}
|
|
|
|
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
|
|
const TargetRegisterInfo *TRI) {
|
|
int Reg = TRI->getLLVMRegNum(DwarfReg, true);
|
|
if (Reg == -1) {
|
|
OS << "<badreg>";
|
|
return;
|
|
}
|
|
printReg(Reg, OS, TRI);
|
|
}
|
|
|
|
void MIPrinter::print(const MCCFIInstruction &CFI,
|
|
const TargetRegisterInfo *TRI) {
|
|
switch (CFI.getOperation()) {
|
|
case MCCFIInstruction::OpOffset:
|
|
OS << ".cfi_offset ";
|
|
if (CFI.getLabel())
|
|
OS << "<mcsymbol> ";
|
|
printCFIRegister(CFI.getRegister(), OS, TRI);
|
|
OS << ", " << CFI.getOffset();
|
|
break;
|
|
case MCCFIInstruction::OpDefCfaRegister:
|
|
OS << ".cfi_def_cfa_register ";
|
|
if (CFI.getLabel())
|
|
OS << "<mcsymbol> ";
|
|
printCFIRegister(CFI.getRegister(), OS, TRI);
|
|
break;
|
|
case MCCFIInstruction::OpDefCfaOffset:
|
|
OS << ".cfi_def_cfa_offset ";
|
|
if (CFI.getLabel())
|
|
OS << "<mcsymbol> ";
|
|
OS << CFI.getOffset();
|
|
break;
|
|
case MCCFIInstruction::OpDefCfa:
|
|
OS << ".cfi_def_cfa ";
|
|
if (CFI.getLabel())
|
|
OS << "<mcsymbol> ";
|
|
printCFIRegister(CFI.getRegister(), OS, TRI);
|
|
OS << ", " << CFI.getOffset();
|
|
break;
|
|
default:
|
|
// TODO: Print the other CFI Operations.
|
|
OS << "<unserializable cfi operation>";
|
|
break;
|
|
}
|
|
}
|
|
|
|
void llvm::printMIR(raw_ostream &OS, const Module &M) {
|
|
yaml::Output Out(OS);
|
|
Out << const_cast<Module &>(M);
|
|
}
|
|
|
|
void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
|
|
MIRPrinter Printer(OS);
|
|
Printer.print(MF);
|
|
}
|