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874371d11b
This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248887 91177308-0d34-0410-b5e6-96231b3b80d8
156 lines
6.6 KiB
LLVM
156 lines
6.6 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
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%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
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%struct.__neon_int16x4x2_t = type { <4 x i16>, <4 x i16> }
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%struct.__neon_int32x2x2_t = type { <2 x i32>, <2 x i32> }
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%struct.__neon_float32x2x2_t = type { <2 x float>, <2 x float> }
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%struct.__neon_int64x1x2_t = type { <1 x i64>, <1 x i64> }
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%struct.__neon_int8x16x2_t = type { <16 x i8>, <16 x i8> }
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%struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> }
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%struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> }
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%struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
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define <8 x i8> @vld2i8(i8* %A) nounwind {
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;CHECK-LABEL: vld2i8:
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;Check the alignment value. Max for this instruction is 128 bits:
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;CHECK: vld2.8 {d16, d17}, [r0:64]
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%tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8.p0i8(i8* %A, i32 8)
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%tmp2 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 1
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%tmp4 = add <8 x i8> %tmp2, %tmp3
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vld2i16(i16* %A) nounwind {
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;CHECK-LABEL: vld2i16:
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;Check the alignment value. Max for this instruction is 128 bits:
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;CHECK: vld2.16 {d16, d17}, [r0:128]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16.p0i8(i8* %tmp0, i32 32)
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%tmp2 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 1
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%tmp4 = add <4 x i16> %tmp2, %tmp3
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vld2i32(i32* %A) nounwind {
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;CHECK-LABEL: vld2i32:
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;CHECK: vld2.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32.p0i8(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 1
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%tmp4 = add <2 x i32> %tmp2, %tmp3
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ret <2 x i32> %tmp4
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}
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define <2 x float> @vld2f(float* %A) nounwind {
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;CHECK-LABEL: vld2f:
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;CHECK: vld2.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0i8(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1
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%tmp4 = fadd <2 x float> %tmp2, %tmp3
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ret <2 x float> %tmp4
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}
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;Check for a post-increment updating load.
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define <2 x float> @vld2f_update(float** %ptr) nounwind {
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;CHECK-LABEL: vld2f_update:
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;CHECK: vld2.32 {d16, d17}, [r1]!
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%A = load float*, float** %ptr
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0i8(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1
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%tmp4 = fadd <2 x float> %tmp2, %tmp3
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%tmp5 = getelementptr float, float* %A, i32 4
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store float* %tmp5, float** %ptr
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ret <2 x float> %tmp4
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}
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define <1 x i64> @vld2i64(i64* %A) nounwind {
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;CHECK-LABEL: vld2i64:
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;Check the alignment value. Max for this instruction is 128 bits:
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;CHECK: vld1.64 {d16, d17}, [r0:128]
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%tmp0 = bitcast i64* %A to i8*
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%tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64.p0i8(i8* %tmp0, i32 32)
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%tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 1
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%tmp4 = add <1 x i64> %tmp2, %tmp3
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ret <1 x i64> %tmp4
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}
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define <16 x i8> @vld2Qi8(i8* %A) nounwind {
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;CHECK-LABEL: vld2Qi8:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64]
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%tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0i8(i8* %A, i32 8)
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%tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
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%tmp4 = add <16 x i8> %tmp2, %tmp3
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ret <16 x i8> %tmp4
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}
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;Check for a post-increment updating load with register increment.
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define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind {
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;CHECK-LABEL: vld2Qi8_update:
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;CHECK: vld2.8 {d16, d17, d18, d19}, [r2:128], r1
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%A = load i8*, i8** %ptr
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%tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0i8(i8* %A, i32 16)
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%tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
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%tmp4 = add <16 x i8> %tmp2, %tmp3
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%tmp5 = getelementptr i8, i8* %A, i32 %inc
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store i8* %tmp5, i8** %ptr
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vld2Qi16(i16* %A) nounwind {
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;CHECK-LABEL: vld2Qi16:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16.p0i8(i8* %tmp0, i32 16)
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%tmp2 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 1
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%tmp4 = add <8 x i16> %tmp2, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vld2Qi32(i32* %A) nounwind {
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;CHECK-LABEL: vld2Qi32:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256]
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8* %tmp0, i32 64)
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%tmp2 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 1
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%tmp4 = add <4 x i32> %tmp2, %tmp3
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ret <4 x i32> %tmp4
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}
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define <4 x float> @vld2Qf(float* %A) nounwind {
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;CHECK-LABEL: vld2Qf:
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;CHECK: vld2.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32.p0i8(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 1
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%tmp4 = fadd <4 x float> %tmp2, %tmp3
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ret <4 x float> %tmp4
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}
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declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8.p0i8(i8*, i32) nounwind readonly
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declare %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16.p0i8(i8*, i32) nounwind readonly
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declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32.p0i8(i8*, i32) nounwind readonly
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declare %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0i8(i8*, i32) nounwind readonly
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declare %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64.p0i8(i8*, i32) nounwind readonly
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declare %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0i8(i8*, i32) nounwind readonly
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declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16.p0i8(i8*, i32) nounwind readonly
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declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8*, i32) nounwind readonly
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declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32.p0i8(i8*, i32) nounwind readonly
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