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f6a4d3c2f3
Add a avoidWriteAfterWrite() target hook to identify register classes that suffer from write-after-write hazards. For those register classes, try to avoid writing the same register in two consecutive instructions. This is currently disabled by default. We should not spill to avoid hazards! The command line flag -avoid-waw-hazard can be used to enable waw avoidance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129772 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
1.2 KiB
LLVM
49 lines
1.2 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=VFP2
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEON
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; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2
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define i32 @test1(float %a, float %b) {
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; VFP2: test1:
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; VFP2: vcvt.s32.f32 s{{.}}, s{{.}}
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; NEON: test1:
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; NEON: vcvt.s32.f32 d0, d0
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entry:
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%0 = fadd float %a, %b
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%1 = fptosi float %0 to i32
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ret i32 %1
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}
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define i32 @test2(float %a, float %b) {
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; VFP2: test2:
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; VFP2: vcvt.u32.f32 s{{.}}, s{{.}}
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; NEON: test2:
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; NEON: vcvt.u32.f32 d0, d0
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entry:
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%0 = fadd float %a, %b
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%1 = fptoui float %0 to i32
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ret i32 %1
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}
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define float @test3(i32 %a, i32 %b) {
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; VFP2: test3:
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; VFP2: vcvt.f32.u32 s{{.}}, s{{.}}
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; NEON: test3:
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; NEON: vcvt.f32.u32 d0, d0
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entry:
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%0 = add i32 %a, %b
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%1 = uitofp i32 %0 to float
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ret float %1
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}
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define float @test4(i32 %a, i32 %b) {
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; VFP2: test4:
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; VFP2: vcvt.f32.s32 s{{.}}, s{{.}}
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; NEON: test4:
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; NEON: vcvt.f32.s32 d0, d0
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entry:
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%0 = add i32 %a, %b
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%1 = sitofp i32 %0 to float
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ret float %1
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}
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