mirror of
https://github.com/RPCSX/llvm.git
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48575f6ea7
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.
Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.
A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.
Work in progress, only A+B are enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
522 lines
20 KiB
C++
522 lines
20 KiB
C++
//===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Base ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMBASEINSTRUCTIONINFO_H
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#define ARMBASEINSTRUCTIONINFO_H
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#include "ARM.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallSet.h"
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namespace llvm {
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class ARMSubtarget;
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class ARMBaseRegisterInfo;
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/// ARMII - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace ARMII {
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enum {
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//===------------------------------------------------------------------===//
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// Instruction Flags.
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//===------------------------------------------------------------------===//
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// This four-bit field describes the addressing mode used.
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AddrModeMask = 0x1f,
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AddrModeNone = 0,
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AddrMode1 = 1,
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AddrMode2 = 2,
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AddrMode3 = 3,
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AddrMode4 = 4,
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AddrMode5 = 5,
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AddrMode6 = 6,
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AddrModeT1_1 = 7,
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AddrModeT1_2 = 8,
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AddrModeT1_4 = 9,
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AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
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AddrModeT2_i12 = 11,
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AddrModeT2_i8 = 12,
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AddrModeT2_so = 13,
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AddrModeT2_pc = 14, // +/- i12 for pc relative data
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AddrModeT2_i8s4 = 15, // i8 * 4
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AddrMode_i12 = 16,
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// Size* - Flags to keep track of the size of an instruction.
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SizeShift = 5,
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SizeMask = 7 << SizeShift,
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SizeSpecial = 1, // 0 byte pseudo or special case.
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Size8Bytes = 2,
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Size4Bytes = 3,
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Size2Bytes = 4,
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// IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
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// and store ops only. Generic "updating" flag is used for ld/st multiple.
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IndexModeShift = 8,
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IndexModeMask = 3 << IndexModeShift,
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IndexModePre = 1,
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IndexModePost = 2,
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IndexModeUpd = 3,
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//===------------------------------------------------------------------===//
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// Instruction encoding formats.
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//
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FormShift = 10,
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FormMask = 0x3f << FormShift,
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// Pseudo instructions
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Pseudo = 0 << FormShift,
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// Multiply instructions
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MulFrm = 1 << FormShift,
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// Branch instructions
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BrFrm = 2 << FormShift,
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BrMiscFrm = 3 << FormShift,
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// Data Processing instructions
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DPFrm = 4 << FormShift,
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DPSoRegFrm = 5 << FormShift,
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// Load and Store
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LdFrm = 6 << FormShift,
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StFrm = 7 << FormShift,
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LdMiscFrm = 8 << FormShift,
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StMiscFrm = 9 << FormShift,
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LdStMulFrm = 10 << FormShift,
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LdStExFrm = 11 << FormShift,
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// Miscellaneous arithmetic instructions
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ArithMiscFrm = 12 << FormShift,
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SatFrm = 13 << FormShift,
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// Extend instructions
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ExtFrm = 14 << FormShift,
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// VFP formats
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VFPUnaryFrm = 15 << FormShift,
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VFPBinaryFrm = 16 << FormShift,
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VFPConv1Frm = 17 << FormShift,
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VFPConv2Frm = 18 << FormShift,
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VFPConv3Frm = 19 << FormShift,
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VFPConv4Frm = 20 << FormShift,
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VFPConv5Frm = 21 << FormShift,
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VFPLdStFrm = 22 << FormShift,
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VFPLdStMulFrm = 23 << FormShift,
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VFPMiscFrm = 24 << FormShift,
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// Thumb format
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ThumbFrm = 25 << FormShift,
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// Miscelleaneous format
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MiscFrm = 26 << FormShift,
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// NEON formats
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NGetLnFrm = 27 << FormShift,
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NSetLnFrm = 28 << FormShift,
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NDupFrm = 29 << FormShift,
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NLdStFrm = 30 << FormShift,
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N1RegModImmFrm= 31 << FormShift,
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N2RegFrm = 32 << FormShift,
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NVCVTFrm = 33 << FormShift,
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NVDupLnFrm = 34 << FormShift,
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N2RegVShLFrm = 35 << FormShift,
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N2RegVShRFrm = 36 << FormShift,
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N3RegFrm = 37 << FormShift,
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N3RegVShFrm = 38 << FormShift,
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NVExtFrm = 39 << FormShift,
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NVMulSLFrm = 40 << FormShift,
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NVTBLFrm = 41 << FormShift,
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//===------------------------------------------------------------------===//
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// Misc flags.
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// UnaryDP - Indicates this is a unary data processing instruction, i.e.
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// it doesn't have a Rn operand.
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UnaryDP = 1 << 16,
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// Xform16Bit - Indicates this Thumb2 instruction may be transformed into
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// a 16-bit Thumb instruction if certain conditions are met.
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Xform16Bit = 1 << 17,
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//===------------------------------------------------------------------===//
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// Code domain.
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DomainShift = 18,
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DomainMask = 3 << DomainShift,
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DomainGeneral = 0 << DomainShift,
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DomainVFP = 1 << DomainShift,
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DomainNEON = 2 << DomainShift,
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//===------------------------------------------------------------------===//
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// Field shifts - such shifts are used to set field while generating
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// machine instructions.
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//
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// FIXME: This list will need adjusting/fixing as the MC code emitter
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// takes shape and the ARMCodeEmitter.cpp bits go away.
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ShiftTypeShift = 4,
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M_BitShift = 5,
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ShiftImmShift = 5,
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ShiftShift = 7,
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N_BitShift = 7,
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ImmHiShift = 8,
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SoRotImmShift = 8,
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RegRsShift = 8,
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ExtRotImmShift = 10,
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RegRdLoShift = 12,
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RegRdShift = 12,
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RegRdHiShift = 16,
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RegRnShift = 16,
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S_BitShift = 20,
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W_BitShift = 21,
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AM3_I_BitShift = 22,
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D_BitShift = 22,
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U_BitShift = 23,
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P_BitShift = 24,
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I_BitShift = 25,
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CondShift = 28
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};
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}
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class ARMBaseInstrInfo : public TargetInstrInfoImpl {
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const ARMSubtarget &Subtarget;
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protected:
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// Can be only subclassed.
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explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
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public:
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// Return the non-pre/post incrementing version of 'Opc'. Return 0
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// if there is not such an opcode.
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virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
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virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables *LV) const;
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virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
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const ARMSubtarget &getSubtarget() const { return Subtarget; }
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ScheduleHazardRecognizer *
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CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II) const;
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// Branch analysis.
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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// Predication support.
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bool isPredicated(const MachineInstr *MI) const {
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int PIdx = MI->findFirstPredOperandIdx();
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return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
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}
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ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
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int PIdx = MI->findFirstPredOperandIdx();
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return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
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: ARMCC::AL;
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}
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virtual
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bool PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const;
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virtual
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bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const;
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virtual bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const;
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virtual bool isPredicable(MachineInstr *MI) const;
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/// GetInstSize - Returns the size of the specified MachineInstr.
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///
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virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
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virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
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int FrameIx,
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uint64_t Offset,
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const MDNode *MDPtr,
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DebugLoc DL) const;
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virtual void reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SubIdx,
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const MachineInstr *Orig,
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const TargetRegisterInfo &TRI) const;
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MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
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virtual bool produceSameValue(const MachineInstr *MI0,
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const MachineInstr *MI1) const;
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/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
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/// determine if two loads are loading from the same base address. It should
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/// only return true if the base pointers are the same and the only
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/// differences between the two addresses is the offset. It also returns the
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/// offsets by reference.
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virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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int64_t &Offset1, int64_t &Offset2)const;
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/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
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/// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
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/// be scheduled togther. On some targets if two loads are loading from
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/// addresses in the same cache line, it's better if they are scheduled
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/// together. This function takes two integers that represent the load offsets
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/// from the common base address. It returns true if it decides it's desirable
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/// to schedule the two loads together. "NumLoads" is the number of loads that
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/// have already been scheduled after Load1.
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virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
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int64_t Offset1, int64_t Offset2,
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unsigned NumLoads) const;
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virtual bool isSchedulingBoundary(const MachineInstr *MI,
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const MachineBasicBlock *MBB,
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const MachineFunction &MF) const;
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virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
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unsigned NumCyles, unsigned ExtraPredCycles,
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float Prob, float Confidence) const;
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virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumT, unsigned ExtraT,
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MachineBasicBlock &FMBB,
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unsigned NumF, unsigned ExtraF,
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float Probability, float Confidence) const;
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virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
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unsigned NumCyles,
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float Probability,
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float Confidence) const {
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return NumCyles == 1;
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}
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/// AnalyzeCompare - For a comparison instruction, return the source register
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/// in SrcReg and the value it compares against in CmpValue. Return true if
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/// the comparison instruction can be analyzed.
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virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
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int &CmpMask, int &CmpValue) const;
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/// OptimizeCompareInstr - Convert the instruction to set the zero flag so
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/// that we can remove a "comparison with zero".
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virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
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int CmpMask, int CmpValue,
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const MachineRegisterInfo *MRI) const;
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/// FoldImmediate - 'Reg' is known to be defined by a move immediate
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/// instruction, try to fold the immediate into the use instruction.
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virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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unsigned Reg, MachineRegisterInfo *MRI) const;
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virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
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const MachineInstr *MI) const;
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virtual
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int getOperandLatency(const InstrItineraryData *ItinData,
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const MachineInstr *DefMI, unsigned DefIdx,
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const MachineInstr *UseMI, unsigned UseIdx) const;
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virtual
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int getOperandLatency(const InstrItineraryData *ItinData,
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SDNode *DefNode, unsigned DefIdx,
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SDNode *UseNode, unsigned UseIdx) const;
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private:
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int getVLDMDefCycle(const InstrItineraryData *ItinData,
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const TargetInstrDesc &DefTID,
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unsigned DefClass,
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unsigned DefIdx, unsigned DefAlign) const;
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int getLDMDefCycle(const InstrItineraryData *ItinData,
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const TargetInstrDesc &DefTID,
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unsigned DefClass,
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unsigned DefIdx, unsigned DefAlign) const;
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int getVSTMUseCycle(const InstrItineraryData *ItinData,
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const TargetInstrDesc &UseTID,
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unsigned UseClass,
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unsigned UseIdx, unsigned UseAlign) const;
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int getSTMUseCycle(const InstrItineraryData *ItinData,
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const TargetInstrDesc &UseTID,
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unsigned UseClass,
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unsigned UseIdx, unsigned UseAlign) const;
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int getOperandLatency(const InstrItineraryData *ItinData,
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const TargetInstrDesc &DefTID,
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unsigned DefIdx, unsigned DefAlign,
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const TargetInstrDesc &UseTID,
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unsigned UseIdx, unsigned UseAlign) const;
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int getInstrLatency(const InstrItineraryData *ItinData,
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const MachineInstr *MI, unsigned *PredCost = 0) const;
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int getInstrLatency(const InstrItineraryData *ItinData,
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SDNode *Node) const;
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bool hasHighOperandLatency(const InstrItineraryData *ItinData,
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const MachineRegisterInfo *MRI,
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const MachineInstr *DefMI, unsigned DefIdx,
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const MachineInstr *UseMI, unsigned UseIdx) const;
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bool hasLowDefLatency(const InstrItineraryData *ItinData,
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const MachineInstr *DefMI, unsigned DefIdx) const;
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private:
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/// Modeling special VFP / NEON fp MLA / MLS hazards.
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/// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
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/// MLx table.
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DenseMap<unsigned, unsigned> MLxEntryMap;
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/// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
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/// stalls when scheduled together with fp MLA / MLS opcodes.
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SmallSet<unsigned, 16> MLxHazardOpcodes;
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public:
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/// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
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/// instruction.
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bool isFpMLxInstruction(unsigned Opcode) const {
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return MLxEntryMap.count(Opcode);
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}
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/// isFpMLxInstruction - This version also returns the multiply opcode and the
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/// addition / subtraction opcode to expand to. Return true for 'HasLane' for
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/// the MLX instructions with an extra lane operand.
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bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
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unsigned &AddSubOpc, bool &NegAcc,
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bool &HasLane) const;
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/// canCauseFpMLxStall - Return true if an instruction of the specified opcode
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/// will cause stalls when scheduled after (within 4-cycle window) a fp
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/// MLA / MLS instruction.
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bool canCauseFpMLxStall(unsigned Opcode) const {
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return MLxHazardOpcodes.count(Opcode);
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}
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};
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static inline
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const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
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return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
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}
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static inline
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const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
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return MIB.addReg(0);
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}
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static inline
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const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
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bool isDead = false) {
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return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
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}
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static inline
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const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
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return MIB.addReg(0);
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}
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static inline
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bool isUncondBranchOpcode(int Opc) {
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return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
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}
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static inline
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bool isCondBranchOpcode(int Opc) {
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return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
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}
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static inline
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bool isJumpTableBranchOpcode(int Opc) {
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return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
|
|
Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
|
|
}
|
|
|
|
static inline
|
|
bool isIndirectBranchOpcode(int Opc) {
|
|
return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
|
|
}
|
|
|
|
/// getInstrPredicate - If instruction is predicated, returns its predicate
|
|
/// condition, otherwise returns AL. It also returns the condition code
|
|
/// register by reference.
|
|
ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
|
|
|
|
int getMatchingCondBranchOpcode(int Opc);
|
|
|
|
/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
|
|
/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
|
|
/// code.
|
|
void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator &MBBI, DebugLoc dl,
|
|
unsigned DestReg, unsigned BaseReg, int NumBytes,
|
|
ARMCC::CondCodes Pred, unsigned PredReg,
|
|
const ARMBaseInstrInfo &TII);
|
|
|
|
void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator &MBBI, DebugLoc dl,
|
|
unsigned DestReg, unsigned BaseReg, int NumBytes,
|
|
ARMCC::CondCodes Pred, unsigned PredReg,
|
|
const ARMBaseInstrInfo &TII);
|
|
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator &MBBI,
|
|
unsigned DestReg, unsigned BaseReg,
|
|
int NumBytes, const TargetInstrInfo &TII,
|
|
const ARMBaseRegisterInfo& MRI,
|
|
DebugLoc dl);
|
|
|
|
|
|
/// rewriteARMFrameIndex / rewriteT2FrameIndex -
|
|
/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
|
|
/// offset could not be handled directly in MI, and return the left-over
|
|
/// portion by reference.
|
|
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
|
|
unsigned FrameReg, int &Offset,
|
|
const ARMBaseInstrInfo &TII);
|
|
|
|
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
|
|
unsigned FrameReg, int &Offset,
|
|
const ARMBaseInstrInfo &TII);
|
|
|
|
} // End llvm namespace
|
|
|
|
#endif
|