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89e60598f6
Summary: For some reason doing executing an MUBUF instruction with the addr64 bit set and a zero base pointer in the resource descriptor causes the memory operation to be dropped when the shader is executed using the HSA runtime. This kind of MUBUF instruction is commonly used when the pointer is stored in VGPRs. The base pointer field in the resource descriptor is set to zero and and the pointer is stored in the vaddr field. This patch resolves the issue by only using flat instructions for global memory operations when targeting HSA. This is an overly conservative fix as all other configurations of MUBUF instructions appear to work. NOTE: re-commit by fixing a failure in Codegen/AMDGPU/llvm.dbg.value.ll Reviewers: tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15543 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256282 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
2.4 KiB
LLVM
58 lines
2.4 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s
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; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa < %s -mattr=-flat-for-global | FileCheck -check-prefix=GCNHSA -check-prefix=CIHSA -check-prefix=ALL %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCNHSA -check-prefix=VIHSA -check-prefix=ALL %s
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; FIXME: align on alloca seems to be ignored for private_segment_alignment
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; ALL-LABEL: {{^}}large_alloca_compute_shader:
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; GCN: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
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; GCN: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
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; GCN: s_mov_b32 s10, -1
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; CI: s_mov_b32 s11, 0x80f000
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; VI: s_mov_b32 s11, 0x800000
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; GCNHSA: .amd_kernel_code_t
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; GCNHSA: compute_pgm_rsrc2_scratch_en = 1
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; GCNHSA: compute_pgm_rsrc2_user_sgpr = 6
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; GCNHSA: compute_pgm_rsrc2_tgid_x_en = 1
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; GCNHSA: compute_pgm_rsrc2_tgid_y_en = 0
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; GCNHSA: compute_pgm_rsrc2_tgid_z_en = 0
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; GCNHSA: compute_pgm_rsrc2_tg_size_en = 0
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; GCNHSA: compute_pgm_rsrc2_tidig_comp_cnt = 0
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; GCNHSA: enable_sgpr_private_segment_buffer = 1
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; GCNHSA: enable_sgpr_dispatch_ptr = 0
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; GCNHSA: enable_sgpr_queue_ptr = 0
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; GCNHSA: enable_sgpr_kernarg_segment_ptr = 1
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; GCNHSA: enable_sgpr_dispatch_id = 0
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; GCNHSA: enable_sgpr_flat_scratch_init = 0
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; GCNHSA: enable_sgpr_private_segment_size = 0
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; GCNHSA: enable_sgpr_grid_workgroup_count_x = 0
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; GCNHSA: enable_sgpr_grid_workgroup_count_y = 0
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; GCNHSA: enable_sgpr_grid_workgroup_count_z = 0
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; GCNHSA: workitem_private_segment_byte_size = 32772
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; GCNHSA: private_segment_alignment = 4
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; GCNHSA: .end_amd_kernel_code_t
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; GCNHSA: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], s7 offen
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; GCNHSA: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], s7 offen
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; Scratch size = alloca size + emergency stack slot
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; ALL: ; ScratchSize: 32772
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define void @large_alloca_compute_shader(i32 %x, i32 %y) #0 {
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%large = alloca [8192 x i32], align 4
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%gep = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 8191
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store volatile i32 %x, i32* %gep
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%gep1 = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 %y
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%val = load volatile i32, i32* %gep1
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store volatile i32 %val, i32 addrspace(1)* undef
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ret void
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}
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attributes #0 = { nounwind }
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