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llvm/test/MC/Disassembler/AMDGPU
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Artem Tamazov d94d7faf07 [AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware registers. 
Possibility to specify code of hardware register kept.
Disassemble to symbolic name, if name is known.
Tests updated/added.

Differential Revision: http://reviews.llvm.org/D19335

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267724 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-27 15:17:03 +00:00
..
dpp_vi.txt [AMDGPU] Disassembler: support for DPP 2016-03-31 14:15:04 +00:00
ds_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00
flat_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00
lit.local.cfg
mov.txt
mubuf_vi.txt [AMDGPU] Fix missing assembler predicates. 2016-03-23 04:27:26 +00:00
nop.txt
smem_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00
smrd_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00
sop1_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00
sop2_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00
sopc_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00
sopk_vi.txt [AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware registers. 2016-04-27 15:17:03 +00:00
sopp_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00
vop1_vi.txt [AMDGPU] Add some VI disassembler tests missing from previous autogeneration due to different filecheck prefix. NFC. 2016-04-08 05:42:20 +00:00
vop1.txt
vop2_vi.txt [AMDGPU] fix readlane/readfirstlane src vgpr operand type. 2016-04-07 13:41:51 +00:00
vop3_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00
vopc_vi.txt [AMDGPU] add VI disassembler tests. NFC. 2016-03-17 17:56:33 +00:00