llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll
Mark Searles 48e0515b4f [AMDGPU] Turn on the new waitcnt insertion pass. Adjust tests.
-enable-si-insert-waitcnts=1 becomes the default
-enable-si-insert-waitcnts=0 to use old pass

Differential Revision: https://reviews.llvm.org/D33730

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304551 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 14:19:25 +00:00

32 lines
1019 B
LLVM

; RUN: llc -march=amdgcn -mcpu=tahiti -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
declare void @llvm.amdgcn.s.dcache.inv() #0
declare void @llvm.amdgcn.s.waitcnt(i32) #0
; GCN-LABEL: {{^}}test_s_dcache_inv:
; GCN-NEXT: ; BB#0:
; SI-NEXT: s_dcache_inv ; encoding: [0x00,0x00,0xc0,0xc7]
; VI-NEXT: s_dcache_inv ; encoding: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00]
; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_s_dcache_inv() #0 {
call void @llvm.amdgcn.s.dcache.inv()
ret void
}
; GCN-LABEL: {{^}}test_s_dcache_inv_insert_wait:
; GCN-NEXT: ; BB#0:
; GCN: s_dcache_inv
; GCN: s_waitcnt lgkmcnt(0) ; encoding
define amdgpu_kernel void @test_s_dcache_inv_insert_wait() #0 {
call void @llvm.amdgcn.s.dcache.inv()
call void @llvm.amdgcn.s.waitcnt(i32 127)
br label %end
end:
store volatile i32 3, i32 addrspace(1)* undef
ret void
}
attributes #0 = { nounwind }