llvm/lib/CodeGen
2013-10-21 20:03:54 +00:00
..
AsmPrinter Fix CodeGen for different size address space GEPs 2013-10-21 20:03:54 +00:00
SelectionDAG Fix CodeGen for different size address space GEPs 2013-10-21 20:03:54 +00:00
AggressiveAntiDepBreaker.cpp Fix crash in AggressiveAntiDepBreaker with empty CriticalPathSet 2013-09-12 04:22:31 +00:00
AggressiveAntiDepBreaker.h Revert "Give internal classes hidden visibility." 2013-09-11 18:05:11 +00:00
AllocationOrder.cpp
AllocationOrder.h Revert "Give internal classes hidden visibility." 2013-09-11 18:05:11 +00:00
Analysis.cpp [stackprotector] Refactor out the end of isInTailCallPosition into the function returnTypeIsEligibleForTailCall. 2013-08-20 08:36:50 +00:00
AntiDepBreaker.h Revert "Give internal classes hidden visibility." 2013-09-11 18:05:11 +00:00
BasicTargetTransformInfo.cpp Costmodel: Add support for horizontal vector reductions 2013-09-17 18:06:50 +00:00
BranchFolding.cpp
BranchFolding.h Revert "Give internal classes hidden visibility." 2013-09-11 18:05:11 +00:00
CalcSpillWeights.cpp
CallingConvLower.cpp Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 2013-07-14 04:42:23 +00:00
CMakeLists.txt Move LiveRegUnits implementation into .cpp. Comment and format. 2013-10-14 20:45:14 +00:00
CodeGen.cpp Remove the now unused strong phi elimination pass. 2013-10-14 16:39:04 +00:00
CriticalAntiDepBreaker.cpp
CriticalAntiDepBreaker.h Revert "Give internal classes hidden visibility." 2013-09-11 18:05:11 +00:00
DeadMachineInstructionElim.cpp
DFAPacketizer.cpp mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr count. 2013-08-23 17:48:33 +00:00
DwarfEHPrepare.cpp
EarlyIfConversion.cpp
EdgeBundles.cpp
ErlangGC.cpp
ExecutionDepsFix.cpp Improve on r192635, ExeDepsFix for avx, and add a test case. 2013-10-15 03:39:43 +00:00
ExpandISelPseudos.cpp
ExpandPostRAPseudos.cpp fix typo in comment 2013-10-11 15:40:14 +00:00
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp
IfConversion.cpp LiveRegUnits: Use *MBB for consistency and convenience. 2013-10-14 22:18:59 +00:00
InlineSpiller.cpp Print register in LiveInterval::print() 2013-10-10 21:29:05 +00:00
InterferenceCache.cpp Represent RegUnit liveness with LiveRange instance 2013-10-10 21:29:02 +00:00
InterferenceCache.h Represent RegUnit liveness with LiveRange instance 2013-10-10 21:29:02 +00:00
IntrinsicLowering.cpp
JITCodeEmitter.cpp
LatencyPriorityQueue.cpp
LexicalScopes.cpp typo. 2013-07-25 17:52:30 +00:00
LiveDebugVariables.cpp Represent RegUnit liveness with LiveRange instance 2013-10-10 21:29:02 +00:00
LiveDebugVariables.h Revert "Give internal classes hidden visibility." 2013-09-11 18:05:11 +00:00
LiveInterval.cpp Print register in LiveInterval::print() 2013-10-10 21:29:05 +00:00
LiveIntervalAnalysis.cpp Print register in LiveInterval::print() 2013-10-10 21:29:05 +00:00
LiveIntervalUnion.cpp
LiveRangeCalc.cpp Work on LiveRange instead of LiveInterval where possible 2013-10-10 21:28:57 +00:00
LiveRangeCalc.h LiveRangeCalc.h: Update a description corresponding to r192396. [-Wdocumentation] 2013-10-11 04:52:03 +00:00
LiveRangeEdit.cpp Represent RegUnit liveness with LiveRange instance 2013-10-10 21:29:02 +00:00
LiveRegMatrix.cpp Represent RegUnit liveness with LiveRange instance 2013-10-10 21:29:02 +00:00
LiveRegUnits.cpp LiveRegUnits: Use *MBB for consistency and convenience. 2013-10-14 22:18:59 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 2013-07-11 16:22:38 +00:00
LLVMBuild.txt
LLVMTargetMachine.cpp Grammar. 2013-10-08 16:47:11 +00:00
LocalStackSlotAllocation.cpp
MachineBasicBlock.cpp Rename LiveRange to LiveInterval::Segment 2013-10-10 21:28:43 +00:00
MachineBlockFrequencyInfo.cpp
MachineBlockPlacement.cpp
MachineBranchProbabilityInfo.cpp
MachineCodeEmitter.cpp
MachineCopyPropagation.cpp
MachineCSE.cpp Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 2013-07-14 04:42:23 +00:00
MachineDominators.cpp
MachineFunction.cpp Use function attributes to indicate that we don't want to realign the stack. 2013-08-01 21:42:05 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp Guard the debug temp variable with NDEBUG to avoid warning/error with NDEBUG defined. 2013-10-15 14:40:46 +00:00
MachineInstrBundle.cpp
MachineLICM.cpp Replace some unnecessary vector copies with references. 2013-09-15 22:04:42 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachinePostDominators.cpp
MachineRegisterInfo.cpp Notify LiveRangeEdit of new virtual registers. 2013-08-14 23:50:09 +00:00
MachineScheduler.cpp Pass LiveQueryResult by value 2013-10-10 21:28:52 +00:00
MachineSink.cpp MachineSink: Fix and tweak critical-edge breaking heuristic. 2013-10-14 16:57:17 +00:00
MachineSSAUpdater.cpp Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 2013-07-14 04:42:23 +00:00
MachineTraceMetrics.cpp
MachineVerifier.cpp Print register in LiveInterval::print() 2013-10-10 21:29:05 +00:00
Makefile
OcamlGC.cpp
OptimizePHIs.cpp
Passes.cpp Remove the now unused strong phi elimination pass. 2013-10-14 16:39:04 +00:00
PeepholeOptimizer.cpp [Peephole] Rewrite copies to avoid cross register banks copies. 2013-09-13 18:26:31 +00:00
PHIElimination.cpp Rename LiveRange to LiveInterval::Segment 2013-10-10 21:28:43 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h Fixed another place in CodeGen where we had a typo in our editor C++ filetype declaration. 2013-08-12 20:52:06 +00:00
PostRASchedulerList.cpp After PostRA scheduling, don't set kill flags on undef operands. 2013-10-16 18:30:23 +00:00
ProcessImplicitDefs.cpp Fix typo 2013-10-04 16:52:58 +00:00
PrologEpilogInserter.cpp Simplify the checking of function attributes by using the simple methods. 2013-09-11 08:35:09 +00:00
PrologEpilogInserter.h Revert "Give internal classes hidden visibility." 2013-09-11 18:05:11 +00:00
PseudoSourceValue.cpp
README.txt
RegAllocBase.cpp Print register in LiveInterval::print() 2013-10-10 21:29:05 +00:00
RegAllocBase.h Revert "Give internal classes hidden visibility." 2013-09-11 18:05:11 +00:00
RegAllocBasic.cpp Track new virtual registers by register number. 2013-08-14 23:50:04 +00:00
RegAllocFast.cpp Explicitly request unsigned enum types when desired 2013-10-08 20:15:11 +00:00
RegAllocGreedy.cpp Represent RegUnit liveness with LiveRange instance 2013-10-10 21:29:02 +00:00
RegAllocPBQP.cpp Track new virtual registers by register number. 2013-08-14 23:50:04 +00:00
RegisterClassInfo.cpp
RegisterCoalescer.cpp Print register in LiveInterval::print() 2013-10-10 21:29:05 +00:00
RegisterCoalescer.h
RegisterPressure.cpp Represent RegUnit liveness with LiveRange instance 2013-10-10 21:29:02 +00:00
RegisterScavenging.cpp RegScavenger should not exclude undef uses 2013-07-11 05:55:57 +00:00
ScheduleDAG.cpp
ScheduleDAGInstrs.cpp Pass LiveQueryResult by value 2013-10-10 21:28:52 +00:00
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp
ShadowStackGC.cpp
ShrinkWrapping.cpp Use reference instead of copy. 2013-09-16 22:03:38 +00:00
SjLjEHPrepare.cpp Reformat code with clang-format. 2013-09-23 20:57:47 +00:00
SlotIndexes.cpp
Spiller.cpp Auto-compute live intervals on demand. 2013-08-14 23:50:16 +00:00
Spiller.h
SpillPlacement.cpp Reapply r185393. 2013-07-16 18:26:15 +00:00
SpillPlacement.h Revert "Give internal classes hidden visibility." 2013-09-11 18:05:11 +00:00
SplitKit.cpp Work on LiveRange instead of LiveInterval where possible 2013-10-10 21:28:57 +00:00
SplitKit.h Revert "Give internal classes hidden visibility." 2013-09-11 18:05:11 +00:00
StackColoring.cpp Rename LiveRange to LiveInterval::Segment 2013-10-10 21:28:43 +00:00
StackProtector.cpp [stackprotector] Refactor the StackProtector pass from a single .cpp file into StackProtector.h and StackProtector.cpp. 2013-09-27 21:58:43 +00:00
StackSlotColoring.cpp Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 2013-07-14 04:42:23 +00:00
TailDuplication.cpp Remove several unused variables. 2013-10-01 13:32:03 +00:00
TargetFrameLoweringImpl.cpp
TargetInstrInfo.cpp IfConverter: Use TargetSchedule for instruction latencies 2013-09-30 15:28:56 +00:00
TargetLoweringBase.cpp CodeGen: Emit a libcall if the target doesn't support 16-byte wide atomics 2013-10-18 08:03:43 +00:00
TargetLoweringObjectFileImpl.cpp [-cxx-abi microsoft] Stick zero initialized symbols into the .bss section for COFF 2013-08-13 01:23:53 +00:00
TargetOptionsImpl.cpp Check only if we have this attribute. If it's not an attribute, then it's assumed false. 2013-08-22 21:16:14 +00:00
TargetRegisterInfo.cpp PrintVRegOrUnit 2013-08-23 17:48:53 +00:00
TargetSchedule.cpp IfConverter: Use TargetSchedule for instruction latencies 2013-09-30 15:28:56 +00:00
TwoAddressInstructionPass.cpp Rename LiveRange to LiveInterval::Segment 2013-10-10 21:28:43 +00:00
UnreachableBlockElim.cpp Remove the very substantial, largely unmaintained legacy PGO 2013-10-02 15:42:23 +00:00
VirtRegMap.cpp [PR16882] Ignore noreturn definitions when setting isPhysRegUsed. 2013-09-25 00:26:17 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.