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NVVMIntrRange adds !range metadata to calls of NVVM intrinsics that return values within known limited range. This allows LLVM to generate optimal code for indexing arrays based on tid/ctaid which is a frequently used pattern in CUDA code. Differential Revision: http://reviews.llvm.org/D20644 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270872 91177308-0d34-0410-b5e6-96231b3b80d8
180 lines
3.6 KiB
C++
180 lines
3.6 KiB
C++
//===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in
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// the LLVM NVPTX back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_NVPTX_NVPTX_H
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#define LLVM_LIB_TARGET_NVPTX_NVPTX_H
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#include "MCTargetDesc/NVPTXBaseInfo.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/IR/Module.h"
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#include "llvm/IR/Value.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetMachine.h"
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#include <cassert>
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#include <iosfwd>
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namespace llvm {
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class NVPTXTargetMachine;
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class FunctionPass;
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class MachineFunctionPass;
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class formatted_raw_ostream;
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namespace NVPTXCC {
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enum CondCodes {
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EQ,
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NE,
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LT,
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LE,
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GT,
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GE
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};
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}
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FunctionPass *createNVPTXISelDag(NVPTXTargetMachine &TM,
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llvm::CodeGenOpt::Level OptLevel);
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ModulePass *createNVPTXAssignValidGlobalNamesPass();
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ModulePass *createGenericToNVVMPass();
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FunctionPass *createNVPTXFavorNonGenericAddrSpacesPass();
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FunctionPass *createNVPTXInferAddressSpacesPass();
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FunctionPass *createNVVMIntrRangePass(unsigned int SmVersion);
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FunctionPass *createNVVMReflectPass();
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FunctionPass *createNVVMReflectPass(const StringMap<int> &Mapping);
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MachineFunctionPass *createNVPTXPrologEpilogPass();
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MachineFunctionPass *createNVPTXReplaceImageHandlesPass();
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FunctionPass *createNVPTXImageOptimizerPass();
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FunctionPass *createNVPTXLowerKernelArgsPass(const NVPTXTargetMachine *TM);
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BasicBlockPass *createNVPTXLowerAllocaPass();
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MachineFunctionPass *createNVPTXPeephole();
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extern Target TheNVPTXTarget32;
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extern Target TheNVPTXTarget64;
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namespace NVPTX {
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enum DrvInterface {
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NVCL,
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CUDA
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};
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// A field inside TSFlags needs a shift and a mask. The usage is
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// always as follows :
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// ((TSFlags & fieldMask) >> fieldShift)
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// The enum keeps the mask, the shift, and all valid values of the
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// field in one place.
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enum VecInstType {
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VecInstTypeShift = 0,
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VecInstTypeMask = 0xF,
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VecNOP = 0,
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VecLoad = 1,
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VecStore = 2,
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VecBuild = 3,
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VecShuffle = 4,
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VecExtract = 5,
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VecInsert = 6,
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VecDest = 7,
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VecOther = 15
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};
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enum SimpleMove {
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SimpleMoveMask = 0x10,
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SimpleMoveShift = 4
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};
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enum LoadStore {
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isLoadMask = 0x20,
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isLoadShift = 5,
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isStoreMask = 0x40,
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isStoreShift = 6
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};
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namespace PTXLdStInstCode {
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enum AddressSpace {
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GENERIC = 0,
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GLOBAL = 1,
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CONSTANT = 2,
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SHARED = 3,
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PARAM = 4,
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LOCAL = 5
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};
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enum FromType {
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Unsigned = 0,
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Signed,
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Float
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};
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enum VecType {
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Scalar = 1,
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V2 = 2,
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V4 = 4
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};
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}
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/// PTXCvtMode - Conversion code enumeration
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namespace PTXCvtMode {
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enum CvtMode {
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NONE = 0,
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RNI,
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RZI,
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RMI,
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RPI,
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RN,
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RZ,
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RM,
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RP,
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BASE_MASK = 0x0F,
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FTZ_FLAG = 0x10,
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SAT_FLAG = 0x20
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};
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}
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/// PTXCmpMode - Comparison mode enumeration
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namespace PTXCmpMode {
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enum CmpMode {
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EQ = 0,
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NE,
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LT,
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LE,
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GT,
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GE,
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LO,
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LS,
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HI,
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HS,
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EQU,
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NEU,
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LTU,
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LEU,
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GTU,
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GEU,
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NUM,
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// NAN is a MACRO
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NotANumber,
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BASE_MASK = 0xFF,
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FTZ_FLAG = 0x100
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};
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}
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}
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} // end namespace llvm;
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// Defines symbolic names for NVPTX registers. This defines a mapping from
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// register name to register number.
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#define GET_REGINFO_ENUM
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#include "NVPTXGenRegisterInfo.inc"
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// Defines symbolic names for the NVPTX instructions.
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#define GET_INSTRINFO_ENUM
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#include "NVPTXGenInstrInfo.inc"
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#endif
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