mirror of
https://github.com/RPCSX/xbyak.git
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patch by whyisthisfieldhere
This commit is contained in:
MITSUNARI Shigeo
parent
b2cc628b44
commit
28f2a1fa97
@ -1322,13 +1322,13 @@ private:
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db(code0 | (reg1.isBit(8) ? 0 : 1)); if (code1 != NONE) db(code1); if (code2 != NONE) db(code2);
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db(getModRM(3, reg1.getIdx(), reg2.getIdx()));
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}
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void opModM(const Address& addr, const Reg& reg, int code0, int code1 = NONE, int code2 = NONE)
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void opModM(const Address& addr, const Reg& reg, int code0, int code1 = NONE, int code2 = NONE, int endOffset = 0)
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{
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if (addr.is64bitDisp()) throw Error(ERR_CANT_USE_64BIT_DISP);
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rex(addr, reg);
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db(code0 | (reg.isBit(8) ? 0 : 1)); if (code1 != NONE) db(code1); if (code2 != NONE) db(code2);
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addr.updateRegField(static_cast<uint8>(reg.getIdx()));
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opAddr(addr);
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opAddr(addr, endOffset);
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}
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void makeJmp(uint32 disp, LabelType type, uint8 shortCode, uint8 longCode, uint8 longPref)
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{
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@ -1377,11 +1377,11 @@ private:
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}
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}
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void opAddr(const Address &addr)
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void opAddr(const Address &addr, int endOffset = 0)
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{
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db(addr.getCode(), static_cast<int>(addr.getSize()));
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if (addr.getLabel()) { // [rip + Label]
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putL_inner(*addr.getLabel(), true, addr.getDisp());
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putL_inner(*addr.getLabel(), true, addr.getDisp() - endOffset);
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}
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}
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/* preCode is for SSSE3/SSE4 */
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@ -1390,7 +1390,7 @@ private:
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if (isValid && !isValid(reg, op)) throw Error(ERR_BAD_COMBINATION);
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if (pref != NONE) db(pref);
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if (op.isMEM()) {
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opModM(static_cast<const Address&>(op), static_cast<const Reg&>(reg), 0x0F, preCode, code);
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opModM(static_cast<const Address&>(op), static_cast<const Reg&>(reg), 0x0F, preCode, code, (imm8 != NONE) ? 1 : 0);
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} else {
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opModR(static_cast<const Reg&>(reg), static_cast<const Reg&>(op), 0x0F, preCode, code);
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}
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@ -1426,14 +1426,14 @@ private:
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opGen(mmx, op, code, 0x66, isXMM_REG32orMEM, imm, B00111010);
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}
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}
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void opR_ModM(const Operand& op, int bit, int ext, int code0, int code1 = NONE, int code2 = NONE, bool disableRex = false)
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void opR_ModM(const Operand& op, int bit, int ext, int code0, int code1 = NONE, int code2 = NONE, bool disableRex = false, int endOffset = 0)
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{
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int opBit = op.getBit();
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if (disableRex && opBit == 64) opBit = 32;
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if (op.isREG(bit)) {
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opModR(Reg(ext, Operand::REG, opBit), static_cast<const Reg&>(op).changeBit(opBit), code0, code1, code2);
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} else if (op.isMEM()) {
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opModM(static_cast<const Address&>(op), Reg(ext, Operand::REG, opBit), code0, code1, code2);
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opModM(static_cast<const Address&>(op), Reg(ext, Operand::REG, opBit), code0, code1, code2, endOffset);
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} else {
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throw Error(ERR_BAD_COMBINATION);
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}
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@ -1441,7 +1441,7 @@ private:
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void opShift(const Operand& op, int imm, int ext)
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{
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verifyMemHasSize(op);
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opR_ModM(op, 0, ext, (B11000000 | ((imm == 1 ? 1 : 0) << 4)));
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opR_ModM(op, 0, ext, (B11000000 | ((imm == 1 ? 1 : 0) << 4)), NONE, NONE, false, (imm != 1) ? 1 : 0);
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if (imm != 1) db(imm);
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}
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void opShift(const Operand& op, const Reg8& cl, int ext)
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@ -1449,12 +1449,12 @@ private:
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if (cl.getIdx() != Operand::CL) throw Error(ERR_BAD_COMBINATION);
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opR_ModM(op, 0, ext, B11010010);
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}
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void opModRM(const Operand& op1, const Operand& op2, bool condR, bool condM, int code0, int code1 = NONE, int code2 = NONE)
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void opModRM(const Operand& op1, const Operand& op2, bool condR, bool condM, int code0, int code1 = NONE, int code2 = NONE, int endOffset = 0)
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{
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if (condR) {
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opModR(static_cast<const Reg&>(op1), static_cast<const Reg&>(op2), code0, code1, code2);
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} else if (condM) {
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opModM(static_cast<const Address&>(op2), static_cast<const Reg&>(op1), code0, code1, code2);
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opModM(static_cast<const Address&>(op2), static_cast<const Reg&>(op1), code0, code1, code2, endOffset);
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} else {
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throw Error(ERR_BAD_COMBINATION);
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}
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@ -1462,7 +1462,7 @@ private:
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void opShxd(const Operand& op, const Reg& reg, uint8 imm, int code, const Reg8 *cl = 0)
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{
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if (cl && cl->getIdx() != Operand::CL) throw Error(ERR_BAD_COMBINATION);
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opModRM(reg, op, (op.isREG(16 | i32e) && op.getBit() == reg.getBit()), op.isMEM() && (reg.isREG(16 | i32e)), 0x0F, code | (cl ? 1 : 0));
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opModRM(reg, op, (op.isREG(16 | i32e) && op.getBit() == reg.getBit()), op.isMEM() && (reg.isREG(16 | i32e)), 0x0F, code | (cl ? 1 : 0), NONE, cl ? 0 : 1);
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if (!cl) db(imm);
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}
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// (REG, REG|MEM), (MEM, REG)
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@ -1487,7 +1487,7 @@ private:
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db(code | 4 | (immBit == 8 ? 0 : 1));
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} else {
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int tmp = immBit < (std::min)(op.getBit(), 32U) ? 2 : 0;
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opR_ModM(op, 0, ext, B10000000 | tmp);
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opR_ModM(op, 0, ext, B10000000 | tmp, NONE, NONE, false, immBit / 8);
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}
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db(imm, immBit / 8);
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}
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@ -1558,7 +1558,7 @@ private:
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{
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db(code1); db(code2 | reg.getIdx());
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}
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void opVex(const Reg& r, const Operand *p1, const Operand *p2, int type, int code, int w)
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void opVex(const Reg& r, const Operand *p1, const Operand *p2, int type, int code, int w, int imm8 = NONE)
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{
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bool x, b;
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if (p2->isMEM()) {
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@ -1578,14 +1578,15 @@ private:
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if (p2->isMEM()) {
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const Address& addr = static_cast<const Address&>(*p2);
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addr.updateRegField(static_cast<uint8>(r.getIdx()));
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opAddr(addr);
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opAddr(addr, (imm8 != NONE) ? 1 : 0);
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} else {
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db(getModRM(3, r.getIdx(), p2->getIdx()));
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}
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if (imm8 != NONE) db(imm8);
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}
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// (r, r, r/m) if isR_R_RM
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// (r, r/m, r)
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void opGpr(const Reg32e& r, const Operand& op1, const Operand& op2, int type, uint8 code, bool isR_R_RM)
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void opGpr(const Reg32e& r, const Operand& op1, const Operand& op2, int type, uint8 code, bool isR_R_RM, int imm8 = NONE)
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{
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const Operand *p1 = &op1;
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const Operand *p2 = &op2;
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@ -1593,9 +1594,9 @@ private:
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const unsigned int bit = r.getBit();
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if (p1->getBit() != bit || (p2->isREG() && p2->getBit() != bit)) throw Error(ERR_BAD_COMBINATION);
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int w = bit == 64;
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opVex(r, p1, p2, type, code, w);
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opVex(r, p1, p2, type, code, w, imm8);
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}
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void opAVX_X_X_XM(const Xmm& x1, const Operand& op1, const Operand& op2, int type, int code0, bool supportYMM, int w = -1)
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void opAVX_X_X_XM(const Xmm& x1, const Operand& op1, const Operand& op2, int type, int code0, bool supportYMM, int w = -1, int imm8 = NONE)
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{
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const Xmm *x2;
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const Operand *op;
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@ -1609,18 +1610,18 @@ private:
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}
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// (x1, x2, op)
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if (!((x1.isXMM() && x2->isXMM()) || (supportYMM && x1.isYMM() && x2->isYMM()))) throw Error(ERR_BAD_COMBINATION);
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opVex(x1, x2, op, type, code0, w);
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opVex(x1, x2, op, type, code0, w, imm8);
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}
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// if cvt then return pointer to Xmm(idx) (or Ymm(idx)), otherwise return op
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void opAVX_X_X_XMcvt(const Xmm& x1, const Operand& op1, const Operand& op2, bool cvt, Operand::Kind kind, int type, int code0, bool supportYMM, int w = -1)
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void opAVX_X_X_XMcvt(const Xmm& x1, const Operand& op1, const Operand& op2, bool cvt, Operand::Kind kind, int type, int code0, bool supportYMM, int w = -1, int imm8 = NONE)
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{
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// use static_cast to avoid calling unintentional copy constructor on gcc
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opAVX_X_X_XM(x1, op1, cvt ? kind == Operand::XMM ? static_cast<const Operand&>(Xmm(op2.getIdx())) : static_cast<const Operand&>(Ymm(op2.getIdx())) : op2, type, code0, supportYMM, w);
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opAVX_X_X_XM(x1, op1, cvt ? kind == Operand::XMM ? static_cast<const Operand&>(Xmm(op2.getIdx())) : static_cast<const Operand&>(Ymm(op2.getIdx())) : op2, type, code0, supportYMM, w, imm8);
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}
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// support (x, x/m, imm), (y, y/m, imm)
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void opAVX_X_XM_IMM(const Xmm& x, const Operand& op, int type, int code, bool supportYMM, int w = -1, int imm = NONE)
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void opAVX_X_XM_IMM (const Xmm& x, const Operand& op, int type, int code, bool supportYMM, int w = -1, int imm8 = NONE)
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{
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opAVX_X_X_XM(x, x.isXMM() ? xm0 : ym0, op, type, code, supportYMM, w); if (imm != NONE) db((uint8)imm);
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opAVX_X_X_XM(x, x.isXMM() ? xm0 : ym0, op, type, code, supportYMM, w, imm8);
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}
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// QQQ:need to refactor
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void opSp1(const Reg& reg, const Operand& op, uint8 pref, uint8 code0, uint8 code1)
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@ -1719,13 +1720,14 @@ public:
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void test(const Operand& op, uint32 imm)
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{
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verifyMemHasSize(op);
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int immSize = (std::min)(op.getBit() / 8, 4U);
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if (op.isREG() && op.getIdx() == 0) { // al, ax, eax
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rex(op);
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db(B10101000 | (op.isBit(8) ? 0 : 1));
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} else {
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opR_ModM(op, 0, 0, B11110110);
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opR_ModM(op, 0, 0, B11110110, NONE, NONE, false, immSize);
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}
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db(imm, (std::min)(op.getBit() / 8, 4U));
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db(imm, immSize);
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}
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void ret(int imm = 0)
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{
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@ -1743,8 +1745,8 @@ public:
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void imul(const Reg& reg, const Operand& op, int imm)
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{
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int s = inner::IsInDisp8(imm) ? 1 : 0;
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opModRM(reg, op, op.isREG() && (reg.getKind() == op.getKind()), op.isMEM(), B01101001 | (s << 1));
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int size = s ? 1 : reg.isREG(16) ? 2 : 4;
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int size = s ? 1 : reg.isREG(16) ? 2 : 4;
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opModRM(reg, op, op.isREG() && (reg.getKind() == op.getKind()), op.isMEM(), B01101001 | (s << 1), NONE, NONE, size);
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db(imm, size);
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}
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void pop(const Operand& op)
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@ -2055,7 +2057,7 @@ public:
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}
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void rdrand(const Reg& r) { if (r.isBit(8)) throw Error(ERR_BAD_SIZE_OF_REGISTER); opModR(Reg(6, Operand::REG, r.getBit()), r, 0x0f, 0xc7); }
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void rdseed(const Reg& r) { if (r.isBit(8)) throw Error(ERR_BAD_SIZE_OF_REGISTER); opModR(Reg(7, Operand::REG, r.getBit()), r, 0x0f, 0xc7); }
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void rorx(const Reg32e& r, const Operand& op, uint8 imm) { opGpr(r, op, Reg32e(0, r.getBit()), MM_0F3A | PP_F2, 0xF0, false); db(imm); }
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void rorx(const Reg32e& r, const Operand& op, uint8 imm) { opGpr(r, op, Reg32e(0, r.getBit()), MM_0F3A | PP_F2, 0xF0, false, imm); }
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enum { NONE = 256 };
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CodeGenerator(size_t maxSize = DEFAULT_MAX_CODE_SIZE, void *userPtr = 0, Allocator *allocator = 0)
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: CodeArray(maxSize, userPtr, allocator)
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