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rebase tests

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Change-Id: Ida6e97d3841e8f33108c56aac3921db14c97358e
This commit is contained in:
Mark Charney 2017-06-24 12:43:03 -04:00 committed by Mark Charney
parent d20b4ac07e
commit 03a1c5f6c1
26 changed files with 26 additions and 26 deletions
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2
tests/tests-base/test-00197/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00198/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00199/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00200/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00201/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00202/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00203/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00204/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00205/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00206/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00207/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00208/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00209/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00210/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00211/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00212/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00213/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00214/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00215/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00216/stdout.reference
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@ -14,7 +14,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 RELBR BRANCH_DISPLACEMENT_BYTES= 1 ffffffaa EXPLICIT R B 8 1 1 8 INT INVALID
1 REG0 REG0=ECX SUPPRESSED RW ASZ 32 4 1 32 INT GPR
2 REG1 REG1=EIP SUPPRESSED RW V 32 4 1 32 INT IP
2 REG1 REG1=EIP SUPPRESSED RW Y 32 4 1 32 INT IP
3 REG2 REG2=EFLAGS SUPPRESSED R Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0

2
tests/tests-base/test-00251/stdout.reference
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@ -13,7 +13,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 MEM0 (see below) EXPLICIT R P2 48 6 1 48 STRUCT INVALID
1 REG0 REG0=STACKPUSH SUPPRESSED W SPW2 64 8 1 64 INT PSEUDO
2 REG1 REG1=RIP SUPPRESSED W V 32 4 1 32 INT IP
2 REG1 REG1=RIP SUPPRESSED W Y 32 4 1 32 INT IP
3 MEM1 (see below) SUPPRESSED W SPW2 64 8 1 64 INT INVALID
4 BASE1 BASE1=RSP SUPPRESSED RW SSZ 64 8 1 64 INT GPR
Memory Operands

2
tests/tests-base/test-00252/stdout.reference
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@ -13,7 +13,7 @@ Operands
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 MEM0 (see below) EXPLICIT R P2 80 10 1 80 STRUCT INVALID
1 REG0 REG0=STACKPUSH SUPPRESSED W SPW2 128 16 1 128 INT PSEUDO
2 REG1 REG1=RIP SUPPRESSED W V 64 8 1 64 INT IP
2 REG1 REG1=RIP SUPPRESSED W Y 64 8 1 64 INT IP
3 MEM1 (see below) SUPPRESSED W SPW2 128 16 1 128 INT INVALID
4 BASE1 BASE1=RSP SUPPRESSED RW SSZ 64 8 1 64 INT GPR
Memory Operands

2
tests/tests-base/test-00262/stdout.reference
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@ -4,7 +4,7 @@ SHORT: jmp rax
Encodable! FFE0
Discrepenacy after re-encoding. dec_len= 3 [66FFE0] enc_olen= 2 [FFE0] for instruction: JMP JMP_GPRv DF64, EASZ:3, EOSZ:3, HAS_MODRM:1, LZCNT, MAX_BYTES:3, MOD:3, MODE:2, MODRM_BYTE:224, NOMINAL_OPCODE:255, NPREFIXES:1, OUTREG:RAX, P4, POS_MODRM:2, POS_NOMINAL_OPCODE:1, PREFIX66, REG:4, REG0:RAX, REG1:RIP, SMODE:2, SRM:7, TZCNT
0 REG0/R/V/EXPLICIT/NT_LOOKUP_FN/GPRV_B
1 REG1/W/V/SUPPRESSED/NT_LOOKUP_FN/RIP
1 REG1/W/Y/SUPPRESSED/NT_LOOKUP_FN/RIP
YDIS: jmp rax
vs Encode request: JMP DF64, EASZ:3, EOSZ:3, HAS_MODRM:1, LZCNT, MAX_BYTES:3, MOD:3, MODE:2, MODRM_BYTE:224, NOMINAL_OPCODE:255, NPREFIXES:1, OUTREG:RAX, P4, POS_MODRM:2, POS_NOMINAL_OPCODE:1, PREFIX66, REG:4, REG0:RAX, REG1:RIP, SMODE:2, SRM:7, TZCNT
OPERAND ORDER: REG0

2
tests/tests-base/test-00407/stdout.reference
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@ -12,7 +12,7 @@ Operands
# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 REG0 REG0=STACKPOP SUPPRESSED R SPW3 48 6 1 48 INT PSEUDO
1 REG1 REG1=EIP SUPPRESSED W V 16 2 1 16 INT IP
1 REG1 REG1=EIP SUPPRESSED W Y 32 4 1 32 INT IP
2 MEM0 (see below) SUPPRESSED R SPW3 48 6 1 48 INT INVALID
3 BASE0 BASE0=ESP SUPPRESSED RW SSZ 32 4 1 32 INT GPR
4 REG2 REG2=EFLAGS SUPPRESSED RW Y 32 4 1 32 INT FLAGS

2
tests/tests-base/test-00408/stdout.reference
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@ -12,7 +12,7 @@ Operands
# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 REG0 REG0=STACKPOP SUPPRESSED R SPW3 96 12 1 96 INT PSEUDO
1 REG1 REG1=EIP SUPPRESSED W V 32 4 1 32 INT IP
1 REG1 REG1=EIP SUPPRESSED W Y 32 4 1 32 INT IP
2 MEM0 (see below) SUPPRESSED R SPW3 96 12 1 96 INT INVALID
3 BASE0 BASE0=ESP SUPPRESSED RW SSZ 32 4 1 32 INT GPR
4 REG2 REG2=EFLAGS SUPPRESSED RW Y 32 4 1 32 INT FLAGS

2
tests/tests-base/test-00414/stdout.reference
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@ -11,7 +11,7 @@ iclass-max-iform-dispatch 1
Operands
# TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS
# ==== ======= === == === ==== ===== ===== ====== ======== ========
0 REG0 REG0=EIP SUPPRESSED W V 32 4 1 32 INT IP
0 REG0 REG0=EIP SUPPRESSED W Y 32 4 1 32 INT IP
1 REG1 REG1=EFLAGS SUPPRESSED W Y 32 4 1 32 INT FLAGS
Memory Operands
MemopBytes = 0