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amdxop: fix ignore of W0 for a bunch of instr.

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* Changed:
    BEXTR_XOP
    BLCFILL
    BLSFILL
    BLCS
    TZMSK
    BLCIC
    BLSIC
    T1MSKC
    BLCMSK
    BLCI

  * Did not change the LPW instr; AMD docs were not as clear for those.
  can revisit.

Change-Id: I984a683025d45e7b2b255ea207383826b77bda6f
This commit is contained in:
Mark Charney 2017-05-31 17:24:31 -04:00 committed by Mark Charney
parent 6a1d1cbc65
commit 11f051d943
1 changed files with 60 additions and 20 deletions
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80
datafiles/amdxop/amd-xop-isa.txt
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@ -935,10 +935,14 @@ ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-0 pf-u af-u zf-mod sf-u of-0 ]
PATTERN: XOPV 0x10 VNP W0 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32()
PATTERN: XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32()
OPERANDS: REG0=GPR32_R():w:d MEM0:r:d IMM0:r:d
PATTERN: XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32()
OPERANDS: REG0=GPRy_R():w:y MEM0:r:y IMM0:r:d
PATTERN: XOPV 0x10 VNP W0 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32()
PATTERN: XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32()
OPERANDS: REG0=GPR32_R():w:d REG1=GPR32_B():r:d IMM0:r:d
PATTERN: XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32()
OPERANDS: REG0=GPRy_R():w:y REG1=GPRy_B():r:y IMM0:r:d
}
@ -950,10 +954,14 @@ ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:y
}
@ -965,10 +973,14 @@ ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:y
}
@ -980,10 +992,14 @@ ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:y
}
@ -995,10 +1011,14 @@ ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:y
}
@ -1010,10 +1030,14 @@ ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:y
}
@ -1025,10 +1049,14 @@ ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:y
}
@ -1040,10 +1068,14 @@ ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
PATTERN: XOPV 0x01 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPRv_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:y
}
@ -1055,10 +1087,14 @@ ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
PATTERN: XOPV 0x02 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
PATTERN: XOPV 0x02 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPRv_B():r:d
PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:y
}
@ -1070,10 +1106,14 @@ ISA_SET: TBM
EXTENSION: TBM
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
PATTERN: XOPV 0x02 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
PATTERN: XOPV 0x02 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPRv_B():r:d
PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRv_B():r:y
}