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disassembly: handling /is4 better
* sometimes the imm8 has a register specifier (/is4) so we like to display the immediate without the register specifier portion. So we have to distinguish the real imm8 bits specified in the operand from the length of the immediate field. * minor clean up of some of the xml tag emitting Change-Id: I510f084e12181514376ea76031073b77f7d7011c (cherry picked from commit 359ab61b052c87dcd82e203c8d7c688c92237969)
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parent
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44fb3a23a1
@ -1,6 +1,6 @@
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/*BEGIN_LEGAL
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Copyright (c) 2016 Intel Corporation
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Copyright (c) 2017 Intel Corporation
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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@ -319,7 +319,10 @@ xed_decoded_inst_get_stack_address_mode_bits(const xed_decoded_inst_t* p) {
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/// Returns the operand width in bits: 8/16/32/64. This is different than
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/// the #xed_operand_values_get_effective_operand_width() which only
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/// returns 16/32/64. This factors in the BYTEOP attribute when computing
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/// its return value. This is a convenience function.
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/// its return value. This function provides a information for that is only
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/// useful for (scalable) GPR-operations. Individual operands have more
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/// specific information available from
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/// #xed_decoded_inst_operand_element_size_bits()
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/// @ingroup DEC
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XED_DLL_EXPORT xed_uint32_t
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xed_decoded_inst_get_operand_width(const xed_decoded_inst_t* p);
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@ -1,6 +1,6 @@
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/*BEGIN_LEGAL
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Copyright (c) 2016 Intel Corporation
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Copyright (c) 2017 Intel Corporation
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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@ -594,8 +594,6 @@ xed_decoded_inst_operand_element_size_bits(
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unsigned int element_size = 0;
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const xed_inst_t* inst = p->_inst;
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const xed_operand_t* o = xed_inst_operand(inst,operand_index);
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//const xed_operand_enum_t op_name = xed_operand_name(o);
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//const xed_reg_enum_t reg = xed_decoded_inst_get_reg(p, op_name);
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const xed_operand_element_xtype_enum_t xtype = xed_operand_xtype(o);
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const xed_operand_type_info_t* q;
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if ( xtype >= XED_OPERAND_XTYPE_LAST)
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170
src/xed-disas.c
170
src/xed-disas.c
@ -1,6 +1,6 @@
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/*BEGIN_LEGAL
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Copyright (c) 2016 Intel Corporation
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Copyright (c) 2017 Intel Corporation
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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@ -279,6 +279,16 @@ static void xed_prefixes(xed_print_info_t* pi,
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pi->emitted=1;
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}
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static void
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xml_print_end(xed_print_info_t* pi,
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char const* s)
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{
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if (pi->format_options.xml_a) {
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xed_pi_strcat(pi,"</");
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xed_pi_strcat(pi,s);
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xed_pi_strcat(pi,">");
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}
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}
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static void
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xed_decoded_inst_dump_common(xed_print_info_t* pi)
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@ -325,8 +335,8 @@ xed_decoded_inst_dump_common(xed_print_info_t* pi)
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xed_prefixes(pi,"data32");
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}
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}
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if (pi->emitted && pi->format_options.xml_a)
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xed_pi_strcat(pi,"</PREFIXES>");
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if (pi->emitted)
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xml_print_end(pi,"PREFIXES");
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if (pi->emitted)
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xed_pi_strcat(pi," ");
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@ -421,8 +431,8 @@ static void print_seg_prefix_for_suppressed_operands(
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pi->blen = xed_strncat_lower(pi->buf,
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xed_reg_enum_t2str(seg),
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pi->blen);
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if (pi->format_options.xml_a)
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xed_pi_strcat(pi,"</REG></OPERAND>");
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xml_print_end(pi,"REG");
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xml_print_end(pi,"OPERAND");
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pi->emitted = 1;
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}
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}
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@ -457,13 +467,6 @@ xml_reg_prefix(xed_print_info_t* pi, xed_reg_enum_t reg)
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xed_get_register_width_bits(reg));
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}
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static void
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xml_reg_suffix(xed_print_info_t* pi)
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{
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if (pi->format_options.xml_a)
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pi->blen = xed_strncat(pi->buf,"</REG>",pi->blen);
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}
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static void
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print_reg(xed_print_info_t* pi,
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xed_reg_enum_t reg)
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@ -487,7 +490,7 @@ print_reg_xml(xed_print_info_t* pi,
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{
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xml_reg_prefix(pi,reg);
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print_reg(pi,reg);
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xml_reg_suffix(pi);
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xml_print_end(pi,"REG");
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}
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@ -603,7 +606,7 @@ print_reg_writemask(
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#if defined(XED_SUPPORTS_AVX512)
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print_write_mask_generic(pi);
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#endif
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xml_reg_suffix(pi);
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xml_print_end(pi,"REG");
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}
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#define XED_SYMBOL_LEN 512
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@ -686,6 +689,14 @@ print_rel_sym(xed_print_info_t* pi,
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}
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}
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static void
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xml_print_imm(xed_print_info_t* pi,
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unsigned int bits)
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{
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if (pi->format_options.xml_a)
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xml_tag_pi(pi, "IMM", bits);
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}
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static void
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print_relbr(xed_print_info_t* pi)
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{
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@ -693,9 +704,8 @@ print_relbr(xed_print_info_t* pi)
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xed_pi_strcat(pi,"<RELBR>");
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print_rel_sym(pi,print_address, branch_displacement);
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if (pi->format_options.xml_a)
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xed_pi_strcat(pi,"</RELBR>");
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xml_print_end(pi,"RELBR");
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}
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static void xed_print_operand( xed_print_info_t* pi )
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@ -839,13 +849,10 @@ static void xed_print_operand( xed_print_info_t* pi )
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if (base == XED_REG_RIP && xed_operand_values_has_memory_displacement(ov))
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print_rel_sym(pi,no_print_address, memory_displacement);
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if (pi->format_options.xml_a) {
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if (xed_operand_name(op) == XED_OPERAND_AGEN)
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xed_pi_strcat(pi,"</AGEN>");
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else
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xed_pi_strcat(pi,"</MEM>");
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}
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if (xed_operand_name(op) == XED_OPERAND_AGEN)
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xml_print_end(pi,"AGEN");
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else
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xml_print_end(pi,"MEM");
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break;
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}
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@ -878,62 +885,58 @@ static void xed_print_operand( xed_print_info_t* pi )
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xed_reg_enum_t2str(base),
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pi->blen);
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xed_pi_strcat(pi,"]");
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if (pi->format_options.xml_a)
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xed_pi_strcat(pi,"</MEM>");
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xml_print_end(pi,"MEM");
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break;
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}
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case XED_OPERAND_IMM0: {
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unsigned int bits = xed3_operand_get_imm_width(pi->p);
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if (pi->format_options.xml_a)
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xml_tag_pi(pi, "IMM", bits);
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if ( xed3_operand_get_imm0signed(pi->p) &&
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pi->format_options.no_sign_extend_signed_immediates == 0 )
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{
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xed_int32_t disp;
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bits = xed_decoded_inst_get_operand_width(pi->p);
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disp = XED_STATIC_CAST(xed_int32_t,
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// sign-extend imm to effective operand width
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xed_int32_t imm;
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unsigned int eff_bits = xed_decoded_inst_get_operand_width(pi->p);
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imm = XED_STATIC_CAST(xed_int32_t,
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xed_operand_values_get_immediate_int64(ov));
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xml_print_imm(pi,eff_bits);
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xed_pi_strcat(pi,"0x");
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pi->blen = xed_itoa_hex_ul(pi->buf+xed_strlen(pi->buf),
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disp,
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bits,
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imm,
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eff_bits,
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leading_zeros,
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pi->blen,
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pi->format_options.lowercase_hex);
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}
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else {
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xed_uint64_t disp = xed_operand_values_get_immediate_uint64(ov);
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// how many bits of imm hold imm values. Sometimes we use upper bits
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// for other things (like register specifiers)
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unsigned int real_bits = xed_decoded_inst_operand_element_size_bits(
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pi->p,
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pi->operand_indx);
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xed_uint64_t imm = xed_operand_values_get_immediate_uint64(ov);
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xml_print_imm(pi, real_bits);
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xed_pi_strcat(pi,"0x");
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pi->blen = xed_itoa_hex_ul(pi->buf+xed_strlen(pi->buf),
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disp,
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bits,
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leading_zeros,
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pi->blen,
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pi->format_options.lowercase_hex);
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imm,
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real_bits,
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leading_zeros,
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pi->blen,
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pi->format_options.lowercase_hex);
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}
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if (pi->format_options.xml_a)
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xed_pi_strcat(pi,"</IMM>");
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xml_print_end(pi,"IMM");
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break;
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}
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case XED_OPERAND_IMM1: { // The ENTER instruction
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xed_uint64_t disp = xed3_operand_get_uimm1(pi->p);
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if (pi->format_options.xml_a)
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xed_pi_strcat(pi,"<IMM bytes=\"8\">");
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xed_uint64_t imm = xed3_operand_get_uimm1(pi->p);
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xml_print_imm(pi, 8);
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xed_pi_strcat(pi,"0x");
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pi->blen = xed_itoa_hex_ul(pi->buf+xed_strlen(pi->buf),
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disp,
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imm,
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8,
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leading_zeros,
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pi->blen,
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pi->format_options.lowercase_hex);
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if (pi->format_options.xml_a)
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xed_pi_strcat(pi,"</IMM>");
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xml_print_end(pi,"IMM");
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break;
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}
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@ -955,9 +958,7 @@ static void xed_print_operand( xed_print_info_t* pi )
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leading_zeros,
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pi->blen,
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pi->format_options.lowercase_hex);
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if (pi->format_options.xml_a)
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xed_pi_strcat(pi,"</PTR>");
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xml_print_end(pi,"PTR");
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break;
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}
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@ -1013,9 +1014,7 @@ static void xed_print_operand( xed_print_info_t* pi )
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xed_print_operand_decorations(pi, op);
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if (pi->format_options.xml_a)
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xed_pi_strcat(pi,"</OPERAND>");
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xml_print_end(pi,"OPERAND");
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}
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@ -1068,9 +1067,7 @@ xed_decoded_inst_dump_intel_format_internal(xed_print_info_t* pi)
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if (pi->format_options.xml_a)
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xed_pi_strcat(pi,"<ICLASS>");
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pi->blen = xed_strncat_lower(pi->buf, instruction_name, pi->blen);
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if (pi->format_options.xml_a)
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xed_pi_strcat(pi,"</ICLASS>");
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xml_print_end(pi,"ICLASS");
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xed_pi_strcat(pi," ");
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/* print the operands */
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@ -1093,16 +1090,13 @@ xed_decoded_inst_dump_intel_format_internal(xed_print_info_t* pi)
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if (pi->format_options.xml_a)
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xed_pi_strcat(pi,"<OPERAND>");
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print_reg_xml(pi,pi->extra_index_operand);
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if (pi->format_options.xml_a)
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xed_pi_strcat(pi,"</OPERAND>");
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xml_print_end(pi,"OPERAND");
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}
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if (pi->format_options.xml_f)
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pi->blen = xml_print_flags(pi->p, pi->buf, pi->blen);
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if (pi->format_options.xml_a)
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xed_pi_strcat(pi,"</INS>");
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xml_print_end(pi,"INS");
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return 1;
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}
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@ -1340,38 +1334,42 @@ xed_decoded_inst_dump_att_format_internal(
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break;
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}
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case XED_OPERAND_IMM0: {
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xed_pi_strcat(pi,"$0x");
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if ( xed3_operand_get_imm0signed(pi->p) &&
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pi->format_options.no_sign_extend_signed_immediates == 0 )
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{
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unsigned int bits = xed_decoded_inst_get_operand_width(pi->p);
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xed_int32_t disp = XED_STATIC_CAST(xed_int32_t,
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// sign-extend imm to effective operand width
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unsigned int eff_bits = xed_decoded_inst_get_operand_width(pi->p);
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xed_int32_t imm = XED_STATIC_CAST(xed_int32_t,
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xed_operand_values_get_immediate_int64(ov));
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xed_pi_strcat(pi,"$0x");
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pi->blen = xed_itoa_hex_ul(pi->buf+xed_strlen(pi->buf),
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disp,
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bits,
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leading_zeros,
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pi->blen,
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pi->format_options.lowercase_hex);
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imm,
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eff_bits,
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leading_zeros,
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pi->blen,
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pi->format_options.lowercase_hex);
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}
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else {
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unsigned int bits = xed3_operand_get_imm_width(pi->p);
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xed_uint64_t disp =xed_operand_values_get_immediate_uint64(ov);
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xed_pi_strcat(pi,"$0x");
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// how many bits of imm hold imm values. Sometimes we use upper bits
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// for other things (like register specifiers)
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unsigned int real_bits = xed_decoded_inst_operand_element_size_bits(
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pi->p,
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pi->operand_indx);
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xed_uint64_t imm =xed_operand_values_get_immediate_uint64(ov);
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pi->blen = xed_itoa_hex_ul(pi->buf+xed_strlen(pi->buf),
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disp,
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bits,
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leading_zeros,
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pi->blen,
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pi->format_options.lowercase_hex);
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imm,
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real_bits,
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leading_zeros,
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pi->blen,
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pi->format_options.lowercase_hex);
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}
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break;
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}
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case XED_OPERAND_IMM1: { // The ENTER instruction
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xed_uint64_t disp = xed3_operand_get_uimm1(pi->p);
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xed_uint64_t imm = xed3_operand_get_uimm1(pi->p);
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xed_pi_strcat(pi,"$0x");
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pi->blen = xed_itoa_hex_ul(pi->buf+xed_strlen(pi->buf),
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disp,
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imm,
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8,
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leading_zeros,
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pi->blen,
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