mirror of
https://github.com/RPCSX/xed.git
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92e0e6956c
Change-Id: Ib55fdafbe91f5c1b0fe4601bb9adbf36650f45d4 (cherry picked from commit 789029d55e10b93b762e0dac70fa4b772246fc33)
106 lines
3.3 KiB
Plaintext
106 lines
3.3 KiB
Plaintext
#BEGIN_LEGAL
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#
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#Copyright (c) 2016 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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# EXTRQ xmm:w:q, imm8, imm8 66 0F 78 /0 ib ib
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# EXTRQ xmm:w:q, xmm:r:w 66 0F 79 /r
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{
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ICLASS : EXTRQ
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CPL : 3
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CATEGORY : BITBYTE
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EXTENSION : SSE4a
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ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION
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PATTERN : 0x0F 0x78 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() UIMM8_1()
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OPERANDS : REG0=XMM_R():w:q IMM0:r:b IMM1:r:b
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PATTERN : 0x0F 0x79 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
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OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:dq
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}
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# INSERTQ xmm:w:q xmm:r:q, imm8, imm8 f2 0f 78 /r ib ib
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# INSERTQ xmm:w:q xmm:r:dq, f2 0f 79 /r
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{
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ICLASS : INSERTQ
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CPL : 3
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CATEGORY : BITBYTE
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EXTENSION : SSE4a
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ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION
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PATTERN : 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()
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OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:q IMM0:r:b IMM1:r:b
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PATTERN : 0x0F 0x79 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
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OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:dq
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}
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# MOVNTSD mem64:w:q, xmm:r:q f2 0f 2b /r
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# MOVNTSS mem32:w:d, xmm:r:d f3 0f 2b /r
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{
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ICLASS : MOVNTSD
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CPL : 3
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CATEGORY : DATAXFER
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EXTENSION : SSE4a
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ATTRIBUTES: NONTEMPORAL
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PATTERN : 0x0F 0x2B f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
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OPERANDS : MEM0:w:q REG0=XMM_R():r:q
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}
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{
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ICLASS : MOVNTSS
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CPL : 3
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CATEGORY : DATAXFER
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EXTENSION : SSE4a
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ATTRIBUTES: NONTEMPORAL
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PATTERN : 0x0F 0x2B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
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OPERANDS : MEM0:w:d REG0=XMM_R():r:d
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}
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#########################################################################################################
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# These next one is not part of SSE4a or SSE5.
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# LZCNT reg16, reg/mem16 F30FBD /r
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# LZCNT reg32, reg/mem32 F30FBD /r
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# LZCNT reg64, reg/mem64 F30FBD /r
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{
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ICLASS : LZCNT
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CPL : 3
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CATEGORY : BITBYTE
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EXTENSION : AMD
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FLAGS : MUST [ cf-mod zf-mod of-u af-u pf-u sf-u ]
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PATTERN : 0x0F 0xBD f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
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OPERANDS : REG0=GPRv_R():w:v MEM0:r:v
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PATTERN : 0x0F 0xBD f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
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OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v
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}
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{
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ICLASS : BSR
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VERSION : 1
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COMMENT : AMD reused 0FBD for LZCNT and made BSR not have a refining prefix. This version replaces the normal version of BSR
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CPL : 3
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CATEGORY : BITBYTE
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EXTENSION : BASE
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ISA_SET : I386
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FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ]
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PATTERN : 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
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OPERANDS : REG0=GPRv_R():cw MEM0:r:v
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PATTERN : 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
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OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
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}
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