mirror of
https://github.com/RPCSX/xed.git
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e7d734962c
Change-Id: I166833daaa56c33eca01bdf7b9aa6e74a490ba9a (cherry picked from commit 1212ba962dff6dfbfa0bd2469327ff447ce59058)
132 lines
3.7 KiB
Python
Executable File
132 lines
3.7 KiB
Python
Executable File
#!/usr/bin/env python
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#BEGIN_LEGAL
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#
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#Copyright (c) 2017 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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from __future__ import print_function
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import re
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import sys
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def die(s):
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sys.stderr.write(s+"\n")
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sys.exit(1)
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class regmap_t(object):
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"""This converts register indices to register enumerations. And
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vice versa. This replaces some clunkier register lookup machinery
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in XED2."""
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def __init__(self, dst, ntname,base,index):
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self.name = dst
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self.ntname = ntname
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self.base_reg = base
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self.index = index
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self.decode_output = ''
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self.encode_output = ''
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def activate(self):
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self.emit_decoder_code()
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self.emit_encoder_code()
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def dump(self):
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print(" DECODER OUTPUT: ", self.decode_output)
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print(" ENCODER OUTPUT: ", self.encode_output)
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def emit_decoder_code(self):
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self.decode_preamble()
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self.decode_emit()
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self.decode_epilogue()
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def emit_encoder_code(self):
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self.encode_preamble()
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self.encode_emit()
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self.encode_epilogue()
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def decode_preamble(self):
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pass
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def decode_emit(self):
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d = {}
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d['base_reg'] = self.base_reg
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d['index'] = self.index
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d['name'] = self.name # bypass OUTREG!
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c = 'ov[XED_OPERAND_%(name)s]= %(base_reg)s + %(index)s'
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self.decode_output += (c%d)
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def decode_epilogue(self):
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self.decode_output += ";"
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def encode_preamble(self):
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pass
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def encode_emit(self):
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d = {}
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d['operand_name'] = self.name
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d['base_reg'] = self.base_reg
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d['index_name'] = self.index
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c = "ov[XED_OPERAND_%(index_name)s]= ov[XED_OPERAND_%(operand_name)s] - %(base_reg)s;"
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self.encode_output += (c%d)
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def encode_epilogue(self):
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pass
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class parse_regmap_t(object):
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def __init__(self):
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self.regmaps = {}
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def read_line(self,line):
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""" Lines have the following very simple format
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XMM_1 XMM0 REGINDEX1
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"""
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a = line.split()
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if len(a) != 3:
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die("Wrong number of fields on line: " + line)
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try:
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(ntname, base, index) = a
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except:
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die("Could not parse " + line)
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regmap = regmap_t('OUTREG', ntname, 'XED_REG_'+base, index)
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regmap.activate()
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if ntname in self.regmaps:
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die("Attempting to duplication regmap " + ntname)
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self.regmaps[ntname] = regmap
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def read_lines(self,lines):
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for line in lines:
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line = re.sub(r'#.*','',line)
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line = line.strip()
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if line:
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self.read_line(line)
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def dump(self):
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for g,v in self.regmaps.items():
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print(g, ": ")
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v.dump()
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print("\n\n")
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if __name__ == "__main__":
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o = regmap_t('OUTREG', 'XMM_1','XED_REG_XMM0','REGIDX1')
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o.activate()
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o.dump()
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p = parse_regmap_t()
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lines = ['XMM_1 XMM0 REGIDX1',
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'XMM_2 XMM0 REGIDX2',
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'YMM_1 YMM0 REGIDX1',
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'YMM_2 YMM0 REGIDX2' ]
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p.read_lines(lines)
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p.dump()
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